From 3cc95fb4be27a3e130563db102ed268876027288 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 21 Apr 2019 21:58:57 +0200
Subject: Add specify parser

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_parser.y | 244 +++++++++++++++++++++++++++++++++----
 1 file changed, 222 insertions(+), 22 deletions(-)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 40968d17a..2e6863302 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -59,7 +59,7 @@ namespace VERILOG_FRONTEND {
 	std::vector<char> case_type_stack;
 	bool do_not_require_port_stubs;
 	bool default_nettype_wire;
-	bool sv_mode, formal_mode, noblackbox_mode, lib_mode, nowb_mode;
+	bool sv_mode, formal_mode, lib_mode, specify_mode;
 	bool noassert_mode, noassume_mode, norestrict_mode;
 	bool assume_asserts_mode, assert_assumes_mode;
 	bool current_wire_rand, current_wire_const;
@@ -94,6 +94,20 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 	delete al;
 }
 
+struct specify_target {
+	char polarity_op;
+	AstNode *dst, *dat;
+};
+
+struct specify_triple {
+	AstNode *t_min, *t_avg, *t_max;
+};
+
+struct specify_rise_fall {
+	specify_triple rise;
+	specify_triple fall;
+};
+
 %}
 
 %name-prefix "frontend_verilog_yy"
@@ -102,10 +116,15 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 	std::string *string;
 	struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
 	std::map<std::string, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
+	struct specify_target *specify_target_ptr;
+	struct specify_triple *specify_triple_ptr;
+	struct specify_rise_fall *specify_rise_fall_ptr;
 	bool boolean;
+	char ch;
 }
 
-%token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE TOK_SVA_LABEL
+%token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
+%token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER
 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
@@ -116,7 +135,8 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
-%token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM
+%token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
+%token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM
 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
@@ -130,6 +150,12 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %type <boolean> opt_signed opt_property unique_case_attr
 %type <al> attr case_attr
 
+%type <specify_target_ptr> specify_target
+%type <specify_triple_ptr> specify_triple
+%type <specify_rise_fall_ptr> specify_rise_fall
+%type <ast> specify_if
+%type <ch> specify_edge
+
 // operator precedence from low to high
 %left OP_LOR
 %left OP_LAND
@@ -539,7 +565,7 @@ module_body:
 
 module_body_stmt:
 	task_func_decl | specify_block |param_decl | localparam_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
-	always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl;
+	always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
 
 checker_decl:
 	TOK_CHECKER TOK_ID ';' {
@@ -697,15 +723,181 @@ task_func_body:
 	task_func_body behavioral_stmt |
 	/* empty */;
 
+/*************************** specify parser ***************************/
+
 specify_block:
-	TOK_SPECIFY specify_item_opt TOK_ENDSPECIFY |
-	TOK_SPECIFY TOK_ENDSPECIFY ;
+	TOK_SPECIFY specify_item_list TOK_ENDSPECIFY;
 
-specify_item_opt:
-	specify_item_opt specify_item |
-	specify_item ;
+specify_item_list:
+	specify_item specify_item_list |
+	/* empty */;
 
 specify_item:
+	specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
+		AstNode *en_expr = $1;
+		char specify_edge = $3;
+		AstNode *src_expr = $4;
+		string *oper = $5;
+		specify_target *target = $6;
+		specify_rise_fall *timing = $9;
+
+		if (specify_edge != 0 && target->dat == nullptr)
+			frontend_verilog_yyerror("Found specify edge but no data spec.\n");
+
+		AstNode *cell = new AstNode(AST_CELL);
+		ast_stack.back()->children.push_back(cell);
+		cell->str = stringf("$specify$%d", autoidx++);
+		cell->children.push_back(new AstNode(AST_CELLTYPE));
+		cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
+
+		char oper_polarity = 0;
+		char oper_type = oper->at(0);
+
+		if (oper->size() == 3) {
+			oper_polarity = oper->at(0);
+			oper_type = oper->at(1);
+		}
+
+		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_type == '*', false, 1)));
+		cell->children.back()->str = "\\FULL";
+
+		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity != 0, false, 1)));
+		cell->children.back()->str = "\\SRC_DST_PEN";
+
+		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(oper_polarity == '+', false, 1)));
+		cell->children.back()->str = "\\SRC_DST_POL";
+
+		cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_min));
+		cell->children.back()->str = "\\T_RISE_MIN";
+
+		cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_avg));
+		cell->children.back()->str = "\\T_RISE_AVG";
+
+		cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_max));
+		cell->children.back()->str = "\\T_RISE_MAX";
+
+		cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_min));
+		cell->children.back()->str = "\\T_FALL_MIN";
+
+		cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_avg));
+		cell->children.back()->str = "\\T_FALL_AVG";
+
+		cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_max));
+		cell->children.back()->str = "\\T_FALL_MAX";
+
+		cell->children.push_back(new AstNode(AST_ARGUMENT, en_expr ? en_expr : AstNode::mkconst_int(1, false, 1)));
+		cell->children.back()->str = "\\EN";
+
+		cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
+		cell->children.back()->str = "\\SRC";
+
+		cell->children.push_back(new AstNode(AST_ARGUMENT, target->dst));
+		cell->children.back()->str = "\\DST";
+
+		if (target->dat)
+		{
+			cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge != 0, false, 1)));
+			cell->children.back()->str = "\\EDGE_EN";
+
+			cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(specify_edge == 'p', false, 1)));
+			cell->children.back()->str = "\\EDGE_POL";
+
+			cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op != 0, false, 1)));
+			cell->children.back()->str = "\\DAT_DST_PEN";
+
+			cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(target->polarity_op == '+', false, 1)));
+			cell->children.back()->str = "\\DAT_DST_POL";
+
+			cell->children.push_back(new AstNode(AST_ARGUMENT, target->dat));
+			cell->children.back()->str = "\\DAT";
+		}
+
+		delete oper;
+		delete target;
+		delete timing;
+	};
+
+specify_if:
+	TOK_IF '(' expr ')' {
+		$$ = $3;
+	} |
+	/* empty */ {
+		$$ = nullptr;
+	};
+
+specify_target:
+	expr {
+		$$ = new specify_target;
+		$$->polarity_op = 0;
+		$$->dst = $1;
+		$$->dat = nullptr;
+	} |
+	'(' expr ':' expr ')'{
+		$$ = new specify_target;
+		$$->polarity_op = 0;
+		$$->dst = $2;
+		$$->dat = $4;
+	} |
+	'(' expr TOK_NEG_INDEXED expr ')'{
+		$$ = new specify_target;
+		$$->polarity_op = '-';
+		$$->dst = $2;
+		$$->dat = $4;
+	} |
+	'(' expr TOK_POS_INDEXED expr ')'{
+		$$ = new specify_target;
+		$$->polarity_op = '+';
+		$$->dst = $2;
+		$$->dat = $4;
+	};
+
+specify_edge:
+	TOK_POSEDGE { $$ = 'p'; } |
+	TOK_NEGEDGE { $$ = 'n'; } |
+	{ $$ = 0; };
+
+specify_rise_fall:
+	specify_triple {
+		$$ = new specify_rise_fall;
+		$$->rise = *$1;
+		$$->fall.t_min = $1->t_min->clone();
+		$$->fall.t_avg = $1->t_avg->clone();
+		$$->fall.t_max = $1->t_max->clone();
+		delete $1;
+	} |
+	'(' specify_triple ',' specify_triple ')' {
+		$$ = new specify_rise_fall;
+		$$->rise = *$2;
+		$$->fall = *$4;
+		delete $2;
+		delete $4;
+	};
+
+specify_triple:
+	expr {
+		$$ = new specify_triple;
+		$$->t_min = $1;
+		$$->t_avg = $1->clone();
+		$$->t_max = $1->clone();
+	} |
+	expr ':' expr ':' expr {
+		$$ = new specify_triple;
+		$$->t_min = $1;
+		$$->t_avg = $3;
+		$$->t_max = $5;
+	};
+
+/******************** ignored specify parser **************************/
+
+ignored_specify_block:
+	TOK_IGNORED_SPECIFY ignored_specify_item_opt TOK_ENDSPECIFY |
+	TOK_IGNORED_SPECIFY TOK_ENDSPECIFY ;
+
+ignored_specify_item_opt:
+	ignored_specify_item_opt ignored_specify_item |
+	ignored_specify_item ;
+
+ignored_specify_item:
 	specparam_declaration
 	// | pulsestyle_declaration
 	// | showcancelled_declaration
@@ -721,13 +913,13 @@ specparam_declaration:
 // and the 'non_opt_range' rule allows index ranges not allowed by 1364-2005
 // exxxxtending this for SV specparam would change this anyhow
 specparam_range:
-	'[' constant_expression ':' constant_expression ']' ;
+	'[' ignspec_constant_expression ':' ignspec_constant_expression ']' ;
 
 list_of_specparam_assignments:
 	specparam_assignment | list_of_specparam_assignments ',' specparam_assignment;
 
 specparam_assignment:
-	TOK_ID '=' constant_mintypmax_expression ;
+	ignspec_id '=' constant_mintypmax_expression ;
 
 /*
 pulsestyle_declaration :
@@ -802,19 +994,19 @@ opt_polarity_operator :
 
 // Good enough for the time being
 specify_input_terminal_descriptor :
-	TOK_ID ;
+	ignspec_id ;
 
 // Good enough for the time being
 specify_output_terminal_descriptor :
-	TOK_ID ;
+	ignspec_id ;
 
 system_timing_declaration :
-	TOK_ID '(' system_timing_args ')' ';' ;
+	ignspec_id '(' system_timing_args ')' ';' ;
 
 system_timing_arg :
-	TOK_POSEDGE TOK_ID |
-	TOK_NEGEDGE TOK_ID |
-	expr ;
+	TOK_POSEDGE ignspec_id |
+	TOK_NEGEDGE ignspec_id |
+	ignspec_expr ;
 
 system_timing_args :
 	system_timing_arg |
@@ -871,19 +1063,27 @@ tzx_path_delay_expression :
 */
 
 path_delay_expression :
-	constant_expression;
+	ignspec_constant_expression;
 
 constant_mintypmax_expression :
-	constant_expression
-	| constant_expression ':' constant_expression ':' constant_expression
+	ignspec_constant_expression
+	| ignspec_constant_expression ':' ignspec_constant_expression ':' ignspec_constant_expression
 	;
 
 // for the time being this is OK, but we may write our own expr here.
 // as I'm not sure it is legal to use a full expr here (probably not)
 // On the other hand, other rules requiring constant expressions also use 'expr'
 // (such as param assignment), so we may leave this as-is, perhaps adding runtime checks for constant-ness
-constant_expression:
-	expr ;
+ignspec_constant_expression:
+	expr { delete $1; };
+
+ignspec_expr:
+	expr { delete $1; };
+
+ignspec_id:
+	TOK_ID { delete $1; };
+
+/**********************************************************************/
 
 param_signed:
 	TOK_SIGNED {
-- 
cgit v1.2.3


From e807e88b607834170692f56a5538b89fd4175a36 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 09:52:47 +0200
Subject: Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog
 std nomenclature

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_parser.y | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 2e6863302..218d6f738 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -771,7 +771,7 @@ specify_item:
 		cell->children.back()->str = "\\T_RISE_MIN";
 
 		cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_avg));
-		cell->children.back()->str = "\\T_RISE_AVG";
+		cell->children.back()->str = "\\T_RISE_TYP";
 
 		cell->children.push_back(new AstNode(AST_PARASET, timing->rise.t_max));
 		cell->children.back()->str = "\\T_RISE_MAX";
@@ -780,7 +780,7 @@ specify_item:
 		cell->children.back()->str = "\\T_FALL_MIN";
 
 		cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_avg));
-		cell->children.back()->str = "\\T_FALL_AVG";
+		cell->children.back()->str = "\\T_FALL_TYP";
 
 		cell->children.push_back(new AstNode(AST_PARASET, timing->fall.t_max));
 		cell->children.back()->str = "\\T_FALL_MAX";
-- 
cgit v1.2.3


From 71c38d9de527e1a8b55ba295df459fbcf2a0fe47 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 23 Apr 2019 15:46:40 +0200
Subject: Add $specrule cells for $setup/$hold/$skew specify rules

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_parser.y | 69 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 67 insertions(+), 2 deletions(-)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 218d6f738..0a41ba581 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -136,7 +136,7 @@ struct specify_rise_fall {
 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
-%token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM
+%token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND
 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
@@ -153,7 +153,7 @@ struct specify_rise_fall {
 %type <specify_target_ptr> specify_target
 %type <specify_triple_ptr> specify_triple
 %type <specify_rise_fall_ptr> specify_rise_fall
-%type <ast> specify_if
+%type <ast> specify_if specify_condition
 %type <ch> specify_edge
 
 // operator precedence from low to high
@@ -815,6 +815,63 @@ specify_item:
 		delete oper;
 		delete target;
 		delete timing;
+	} |
+	TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' expr ')' ';' {
+		bool limit_gt = false;
+		if (*$1 == "$setup" || *$1 == "$hold")
+			limit_gt = true;
+		else if (*$1 == "$skew")
+			limit_gt = false;
+		else
+			frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
+
+		AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
+		AstNode *src_pol = AstNode::mkconst_int($3 == 'p', false, 1);
+		AstNode *src_expr = $4, *src_en = $5 ? $5 : AstNode::mkconst_int(1, false, 1);
+
+		AstNode *dst_pen = AstNode::mkconst_int($7 != 0, false, 1);
+		AstNode *dst_pol = AstNode::mkconst_int($7 == 'p', false, 1);
+		AstNode *dst_expr = $8, *dst_en = $9 ? $9 : AstNode::mkconst_int(1, false, 1);
+
+		AstNode *limit = $11;
+
+		AstNode *cell = new AstNode(AST_CELL);
+		ast_stack.back()->children.push_back(cell);
+		cell->str = stringf("$specify$%d", autoidx++);
+		cell->children.push_back(new AstNode(AST_CELLTYPE));
+		cell->children.back()->str = "$specrule";
+
+		cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
+		cell->children.back()->str = "\\SRC_EN";
+
+		cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
+		cell->children.back()->str = "\\SRC";
+
+		cell->children.push_back(new AstNode(AST_PARASET, src_pen));
+		cell->children.back()->str = "\\SRC_PEN";
+
+		cell->children.push_back(new AstNode(AST_PARASET, src_pol));
+		cell->children.back()->str = "\\SRC_POL";
+
+		cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
+		cell->children.back()->str = "\\DST_EN";
+
+		cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
+		cell->children.back()->str = "\\DST";
+
+		cell->children.push_back(new AstNode(AST_PARASET, dst_pen));
+		cell->children.back()->str = "\\DST_PEN";
+
+		cell->children.push_back(new AstNode(AST_PARASET, dst_pol));
+		cell->children.back()->str = "\\DST_POL";
+
+		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(limit_gt, false, 1)));
+		cell->children.back()->str = "\\LIMIT_GT";
+
+		cell->children.push_back(new AstNode(AST_PARASET, limit));
+		cell->children.back()->str = "\\T_LIMIT";
+
+		delete $1;
 	};
 
 specify_if:
@@ -825,6 +882,14 @@ specify_if:
 		$$ = nullptr;
 	};
 
+specify_condition:
+	TOK_SPECIFY_AND expr {
+		$$ = $2;
+	} |
+	/* empty */ {
+		$$ = nullptr;
+	};
+
 specify_target:
 	expr {
 		$$ = new specify_target;
-- 
cgit v1.2.3


From 4575e4ad86494e99dd05200f7242dfa632053c78 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 23 Apr 2019 22:18:04 +0200
Subject: Improve $specrule interface

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_parser.y | 38 ++++++++++++++++++--------------------
 1 file changed, 18 insertions(+), 20 deletions(-)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 0a41ba581..13ff1d38b 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -817,12 +817,7 @@ specify_item:
 		delete timing;
 	} |
 	TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' expr ')' ';' {
-		bool limit_gt = false;
-		if (*$1 == "$setup" || *$1 == "$hold")
-			limit_gt = true;
-		else if (*$1 == "$skew")
-			limit_gt = false;
-		else
+		if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$skew")
 			frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
 
 		AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
@@ -841,11 +836,14 @@ specify_item:
 		cell->children.push_back(new AstNode(AST_CELLTYPE));
 		cell->children.back()->str = "$specrule";
 
-		cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
-		cell->children.back()->str = "\\SRC_EN";
+		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(*$1 == "$skew", false, 1)));
+		cell->children.back()->str = "\\SKEW";
 
-		cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
-		cell->children.back()->str = "\\SRC";
+		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(*$1 == "$hold", false, 1)));
+		cell->children.back()->str = "\\HOLD";
+
+		cell->children.push_back(new AstNode(AST_PARASET, limit));
+		cell->children.back()->str = "\\T_LIMIT";
 
 		cell->children.push_back(new AstNode(AST_PARASET, src_pen));
 		cell->children.back()->str = "\\SRC_PEN";
@@ -853,23 +851,23 @@ specify_item:
 		cell->children.push_back(new AstNode(AST_PARASET, src_pol));
 		cell->children.back()->str = "\\SRC_POL";
 
-		cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
-		cell->children.back()->str = "\\DST_EN";
-
-		cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
-		cell->children.back()->str = "\\DST";
-
 		cell->children.push_back(new AstNode(AST_PARASET, dst_pen));
 		cell->children.back()->str = "\\DST_PEN";
 
 		cell->children.push_back(new AstNode(AST_PARASET, dst_pol));
 		cell->children.back()->str = "\\DST_POL";
 
-		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(limit_gt, false, 1)));
-		cell->children.back()->str = "\\LIMIT_GT";
+		cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
+		cell->children.back()->str = "\\SRC_EN";
 
-		cell->children.push_back(new AstNode(AST_PARASET, limit));
-		cell->children.back()->str = "\\T_LIMIT";
+		cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
+		cell->children.back()->str = "\\SRC";
+
+		cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
+		cell->children.back()->str = "\\DST_EN";
+
+		cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
+		cell->children.back()->str = "\\DST";
 
 		delete $1;
 	};
-- 
cgit v1.2.3


From 64925b4e8f7890f5447d9655b2c69dd59a93f7cd Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 23 Apr 2019 22:57:10 +0200
Subject: Improve $specrule interface

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_parser.y | 26 ++++++++++++++++++--------
 1 file changed, 18 insertions(+), 8 deletions(-)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 13ff1d38b..351f38101 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -153,7 +153,7 @@ struct specify_rise_fall {
 %type <specify_target_ptr> specify_target
 %type <specify_triple_ptr> specify_triple
 %type <specify_rise_fall_ptr> specify_rise_fall
-%type <ast> specify_if specify_condition
+%type <ast> specify_if specify_condition specify_opt_arg
 %type <ch> specify_edge
 
 // operator precedence from low to high
@@ -816,8 +816,9 @@ specify_item:
 		delete target;
 		delete timing;
 	} |
-	TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' expr ')' ';' {
-		if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$skew")
+	TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' expr specify_opt_arg ')' ';' {
+		if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$setuphold" && *$1 != "$removal" && *$1 != "$recovery" &&
+				*$1 != "$recrem" && *$1 != "$skew" && *$1 != "$timeskew" && *$1 != "$fullskew" && *$1 != "$nochange")
 			frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
 
 		AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
@@ -829,6 +830,7 @@ specify_item:
 		AstNode *dst_expr = $8, *dst_en = $9 ? $9 : AstNode::mkconst_int(1, false, 1);
 
 		AstNode *limit = $11;
+		AstNode *limit2 = $12;
 
 		AstNode *cell = new AstNode(AST_CELL);
 		ast_stack.back()->children.push_back(cell);
@@ -836,15 +838,15 @@ specify_item:
 		cell->children.push_back(new AstNode(AST_CELLTYPE));
 		cell->children.back()->str = "$specrule";
 
-		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(*$1 == "$skew", false, 1)));
-		cell->children.back()->str = "\\SKEW";
-
-		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(*$1 == "$hold", false, 1)));
-		cell->children.back()->str = "\\HOLD";
+		cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));
+		cell->children.back()->str = "\\TYPE";
 
 		cell->children.push_back(new AstNode(AST_PARASET, limit));
 		cell->children.back()->str = "\\T_LIMIT";
 
+		cell->children.push_back(new AstNode(AST_PARASET, limit2 ? limit2 : AstNode::mkconst_int(0, true)));
+		cell->children.back()->str = "\\T_LIMIT2";
+
 		cell->children.push_back(new AstNode(AST_PARASET, src_pen));
 		cell->children.back()->str = "\\SRC_PEN";
 
@@ -872,6 +874,14 @@ specify_item:
 		delete $1;
 	};
 
+specify_opt_arg:
+	',' expr {
+		$$ = $2;
+	} |
+	/* empty */ {
+		$$ = nullptr;
+	};
+
 specify_if:
 	TOK_IF '(' expr ')' {
 		$$ = $3;
-- 
cgit v1.2.3


From ac10e7d96da4965751fd60a8dd42a8998c011c39 Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Fri, 3 May 2019 03:10:43 +0300
Subject: Initial implementation of elaboration system tasks (IEEE1800-2017
 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at
 elaboration time** within a generate block. This is very useful to stop a
 synthesis of a parametrized block when an illegal combination of parameters
 is chosen.

---
 frontends/verilog/verilog_parser.y | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 40968d17a..1965f090e 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -105,7 +105,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 	bool boolean;
 }
 
-%token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE TOK_SVA_LABEL
+%token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE TOK_SVA_LABEL TOK_ELAB_TASK
 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
@@ -1869,6 +1869,15 @@ gen_stmt:
 		if ($6 != NULL)
 			delete $6;
 		ast_stack.pop_back();
+	} |
+	TOK_ELAB_TASK {
+		AstNode *node = new AstNode(AST_TECALL);
+		node->str = *$1;
+		delete $1;
+		ast_stack.back()->children.push_back(node);
+		ast_stack.push_back(node);
+	} opt_arg_list ';'{
+		ast_stack.pop_back();		
 	};
 
 gen_stmt_block:
-- 
cgit v1.2.3


From 9804c86e87ec83edd29d224f01311b6ae1d41181 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 4 May 2019 07:52:51 +0200
Subject: Add approximate support for SV "var" keyword, fixes #987

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_parser.y | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 40968d17a..f011e07ea 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -110,7 +110,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
-%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT
+%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR
 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG TOK_LOGIC
 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
@@ -456,6 +456,9 @@ wire_type_token:
 	TOK_LOGIC {
 		astbuf3->is_logic = true;
 	} |
+	TOK_VAR {
+		astbuf3->is_logic = true;
+	} |
 	TOK_INTEGER {
 		astbuf3->is_reg = true;
 		astbuf3->range_left = 31;
-- 
cgit v1.2.3


From 66d6ca2de2e31d7c0460ae314b61136e42ded8c5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 4 May 2019 09:25:32 +0200
Subject: Add support for SVA "final" keyword

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_parser.y | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 40968d17a..9edb61a39 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -106,7 +106,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 }
 
 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE TOK_SVA_LABEL
-%token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER
+%token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
@@ -1341,6 +1341,9 @@ opt_property:
 	TOK_PROPERTY {
 		$$ = true;
 	} |
+	TOK_FINAL {
+		$$ = false;
+	} |
 	/* empty */ {
 		$$ = false;
 	};
-- 
cgit v1.2.3


From a98069d76284ac31fd6652236ab40ecc3f584816 Mon Sep 17 00:00:00 2001
From: Ben Widawsky <ben@bwidawsk.net>
Date: Sun, 5 May 2019 19:29:11 -0700
Subject: verilog_parser: Fix Bison warning
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

As of Bison 2.6, name-prefix is deprecated. This fixes
frontends/verilog/verilog_parser.y:99.1-34: warning: deprecated directive, use ‘%define api.prefix {frontend_verilog_yy}’ [-Wdeprecated]
 %name-prefix "frontend_verilog_yy"

For details: https://www.gnu.org/software/bison/manual/html_node/Multiple-Parsers.html

Compile tested only.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 frontends/verilog/verilog_parser.y | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 08377ad9a..46b3a9025 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -96,7 +96,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 
 %}
 
-%name-prefix "frontend_verilog_yy"
+%define api.prefix {frontend_verilog_yy}
 
 %union {
 	std::string *string;
-- 
cgit v1.2.3


From 8eb2798776ef83afd187d65b8eb471a4b2f3c219 Mon Sep 17 00:00:00 2001
From: Henner Zeller <h.zeller@acm.org>
Date: Tue, 14 May 2019 21:07:26 -0700
Subject: Make the generated *.tab.hh include all the headers needed to define
 the union.

---
 frontends/verilog/verilog_parser.y | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index d23009e60..e82c2781c 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -112,6 +112,15 @@ struct specify_rise_fall {
 
 %define api.prefix {frontend_verilog_yy}
 
+/* The union is defined in the header, so we need to provide all the
+ * includes it requires
+ */
+%code requires {
+#include <map>
+#include <string>
+#include "frontends/verilog/verilog_frontend.h"
+}
+
 %union {
 	std::string *string;
 	struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
@@ -2418,4 +2427,3 @@ concat_list:
 		$$ = $3;
 		$$->children.push_back($1);
 	};
-
-- 
cgit v1.2.3


From ce4a0954bc896eedfc2d87e2c9d2b40f42a101db Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Thu, 16 May 2019 12:44:16 +0200
Subject: Added support for parsing attributes on parameters in Verilog
 frontent. Content of those attributes is ignored.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 frontends/verilog/verilog_parser.y | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index d23009e60..ce1eb31d8 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1193,7 +1193,7 @@ param_range:
 	};
 
 param_decl:
-	TOK_PARAMETER {
+	attr TOK_PARAMETER {
 		astbuf1 = new AstNode(AST_PARAMETER);
 		astbuf1->children.push_back(AstNode::mkconst_int(0, true));
 	} param_signed param_integer param_real param_range param_decl_list ';' {
@@ -1201,7 +1201,7 @@ param_decl:
 	};
 
 localparam_decl:
-	TOK_LOCALPARAM {
+	attr TOK_LOCALPARAM {
 		astbuf1 = new AstNode(AST_LOCALPARAM);
 		astbuf1->children.push_back(AstNode::mkconst_int(0, true));
 	} param_signed param_integer param_real param_range param_decl_list ';' {
-- 
cgit v1.2.3


From 9df04d7e7520884bfc40004bb131cfdb474061c7 Mon Sep 17 00:00:00 2001
From: Stefan Biereigel <stefan.biereigel@cern.ch>
Date: Wed, 22 May 2019 14:22:42 +0200
Subject: make lexer/parser aware of wand/wor net types

---
 frontends/verilog/verilog_parser.y | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 132468f0c..8800705ac 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -139,7 +139,7 @@ struct specify_rise_fall {
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
 %token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR
-%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG TOK_LOGIC
+%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
@@ -485,6 +485,12 @@ wire_type_token_io:
 wire_type_token:
 	TOK_WIRE {
 	} |
+	TOK_WOR {
+        astbuf3->is_wor = true;
+	} |
+	TOK_WAND {
+        astbuf3->is_wand = true;
+	} |
 	TOK_REG {
 		astbuf3->is_reg = true;
 	} |
-- 
cgit v1.2.3


From fd003e0e975be3c7f357fb151fd1c83a8ea9b0ae Mon Sep 17 00:00:00 2001
From: Stefan Biereigel <stefan.biereigel@cern.ch>
Date: Thu, 23 May 2019 13:42:30 +0200
Subject: fix indentation across files

---
 frontends/verilog/verilog_parser.y | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 8800705ac..8244a8f44 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -486,10 +486,10 @@ wire_type_token:
 	TOK_WIRE {
 	} |
 	TOK_WOR {
-        astbuf3->is_wor = true;
+		astbuf3->is_wor = true;
 	} |
 	TOK_WAND {
-        astbuf3->is_wand = true;
+		astbuf3->is_wand = true;
 	} |
 	TOK_REG {
 		astbuf3->is_reg = true;
-- 
cgit v1.2.3


From a6cadf6318f4eff6197d6c6f0e052c2417689f38 Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Fri, 31 May 2019 12:24:12 +0200
Subject: Added support for parsing attributes on port connections.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 frontends/verilog/verilog_parser.y | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 8244a8f44..82a1d9d39 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1532,27 +1532,27 @@ cell_port_list_rules:
 	cell_port | cell_port_list_rules ',' cell_port;
 
 cell_port:
-	/* empty */ {
+	attr {
 		AstNode *node = new AstNode(AST_ARGUMENT);
 		astbuf2->children.push_back(node);
 	} |
-	expr {
+	attr expr {
 		AstNode *node = new AstNode(AST_ARGUMENT);
 		astbuf2->children.push_back(node);
-		node->children.push_back($1);
+		node->children.push_back($2);
 	} |
-	'.' TOK_ID '(' expr ')' {
+	attr '.' TOK_ID '(' expr ')' {
 		AstNode *node = new AstNode(AST_ARGUMENT);
-		node->str = *$2;
+		node->str = *$3;
 		astbuf2->children.push_back(node);
-		node->children.push_back($4);
-		delete $2;
+		node->children.push_back($5);
+		delete $3;
 	} |
-	'.' TOK_ID '(' ')' {
+	attr '.' TOK_ID '(' ')' {
 		AstNode *node = new AstNode(AST_ARGUMENT);
-		node->str = *$2;
+		node->str = *$3;
 		astbuf2->children.push_back(node);
-		delete $2;
+		delete $3;
 	};
 
 always_stmt:
-- 
cgit v1.2.3


From 03e0d3a17cf27858d16e0169614b6575c7dac538 Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Wed, 5 Jun 2019 10:42:43 +0200
Subject: Fixed memory leak.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 frontends/verilog/verilog_parser.y | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 82a1d9d39..ccdab987f 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1535,11 +1535,13 @@ cell_port:
 	attr {
 		AstNode *node = new AstNode(AST_ARGUMENT);
 		astbuf2->children.push_back(node);
+		free_attr($1);
 	} |
 	attr expr {
 		AstNode *node = new AstNode(AST_ARGUMENT);
 		astbuf2->children.push_back(node);
 		node->children.push_back($2);
+		free_attr($1);
 	} |
 	attr '.' TOK_ID '(' expr ')' {
 		AstNode *node = new AstNode(AST_ARGUMENT);
@@ -1547,12 +1549,14 @@ cell_port:
 		astbuf2->children.push_back(node);
 		node->children.push_back($5);
 		delete $3;
+		free_attr($1);
 	} |
 	attr '.' TOK_ID '(' ')' {
 		AstNode *node = new AstNode(AST_ARGUMENT);
 		node->str = *$3;
 		astbuf2->children.push_back(node);
 		delete $3;
+		free_attr($1);
 	};
 
 always_stmt:
-- 
cgit v1.2.3


From 88f59770932720cfc1e987c98e53faedd7388ed8 Mon Sep 17 00:00:00 2001
From: tux3 <barrdetwix@gmail.com>
Date: Wed, 5 Jun 2019 00:47:54 +0200
Subject: SystemVerilog support for implicit named port connections

This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
---
 frontends/verilog/verilog_parser.y | 26 +++++++++++++++++---------
 1 file changed, 17 insertions(+), 9 deletions(-)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 8244a8f44..983445011 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -154,7 +154,7 @@ struct specify_rise_fall {
 %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
 
 %type <ast> range range_or_multirange  non_opt_range non_opt_multirange range_or_signed_int
-%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
+%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list named_port
 %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id
 %type <boolean> opt_signed opt_property unique_case_attr
 %type <al> attr case_attr
@@ -1541,18 +1541,26 @@ cell_port:
 		astbuf2->children.push_back(node);
 		node->children.push_back($1);
 	} |
-	'.' TOK_ID '(' expr ')' {
-		AstNode *node = new AstNode(AST_ARGUMENT);
-		node->str = *$2;
-		astbuf2->children.push_back(node);
-		node->children.push_back($4);
-		delete $2;
+	named_port '(' ')' | // not connected
+	named_port '(' expr ')' {
+		($1)->children.push_back($3);
 	} |
-	'.' TOK_ID '(' ')' {
+	named_port {
+		// SV implied port
+		if (!sv_mode)
+			frontend_verilog_yyerror("Implicit .name port connection in port list (%s). This is not supported unless read_verilog is called with -sv!", $1->str.c_str());
+		auto id_node = new AstNode(AST_IDENTIFIER);
+		id_node->str = ($1)->str;
+		($1)->children.push_back(id_node);
+	};
+
+named_port:
+	'.' TOK_ID {
 		AstNode *node = new AstNode(AST_ARGUMENT);
 		node->str = *$2;
-		astbuf2->children.push_back(node);
 		delete $2;
+		astbuf2->children.push_back(node);
+		$$ = node;
 	};
 
 always_stmt:
-- 
cgit v1.2.3


From a0b57f2a6ffae3b5770e38bf5a9af0df50db8522 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 7 Jun 2019 11:46:16 +0200
Subject: Cleanup tux3-implicit_named_connection

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_parser.y | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 2fffc7536..6d3afed0e 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -154,7 +154,7 @@ struct specify_rise_fall {
 %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
 
 %type <ast> range range_or_multirange  non_opt_range non_opt_multirange range_or_signed_int
-%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list named_port
+%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
 %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id
 %type <boolean> opt_signed opt_property unique_case_attr
 %type <al> attr case_attr
-- 
cgit v1.2.3