From 8b8af10f5e612eb1a39320e20b2d1d6f1e7d45df Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tobias=20W=C3=B6lfel?= Date: Wed, 19 Jun 2019 12:47:48 +0200 Subject: Unpacked array declaration using size Allows fixed-sized array dimension specified by a single number. This commit is based on the work from PeterCrozier https://github.com/YosysHQ/yosys/pull/560. But is split out of the original work. --- frontends/verilog/verilog_parser.y | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'frontends/verilog') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index a034f9601..f77321f09 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1385,7 +1385,13 @@ wire_name: node->children.push_back(rng); } node->type = AST_MEMORY; - node->children.push_back($2); + auto *rangeNode = $2; + if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) { + // SV array size [n], rewrite as [n-1:0] + rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true)); + rangeNode->children.push_back(AstNode::mkconst_int(0, false)); + } + node->children.push_back(rangeNode); } if (current_function_or_task == NULL) { if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) { -- cgit v1.2.3