From 6c84341f22b2758181164e8d5cddd23e3589c90b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 2 Jul 2015 11:14:30 +0200 Subject: Fixed trailing whitespaces --- frontends/vhdl2verilog/vhdl2verilog.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'frontends/vhdl2verilog') diff --git a/frontends/vhdl2verilog/vhdl2verilog.cc b/frontends/vhdl2verilog/vhdl2verilog.cc index 82ff7b502..80bf243f0 100644 --- a/frontends/vhdl2verilog/vhdl2verilog.cc +++ b/frontends/vhdl2verilog/vhdl2verilog.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -178,6 +178,6 @@ struct Vhdl2verilogPass : public Pass { log_pop(); } } Vhdl2verilogPass; - + YOSYS_NAMESPACE_END -- cgit v1.2.3