From dbfd8460a9f1d24d1c8893dfae7dd272d17a7b6f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 29 Sep 2017 11:56:43 +0200 Subject: Allow $size and $bits in verilog mode, actually check test case --- frontends/ast/simplify.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 678951850..cd2120b8c 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1870,7 +1870,7 @@ skip_dynamic_range_lvalue_expansion:; goto apply_newNode; } - if (VERILOG_FRONTEND::sv_mode && (str == "\\$size" || str == "\\$bits")) + if (str == "\\$size" || str == "\\$bits") { if (str == "\\$bits" && children.size() != 1) log_error("System function %s got %d arguments, expected 1 at %s:%d.\n", -- cgit v1.2.3