From 7203ba7bc1d83777bd2c2c347d45209d8e3d4b84 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Wed, 2 Nov 2022 17:12:51 +0100 Subject: Add bitwise `$bweqx` and `$bwmux` cells The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`) cells enable compact encoding and decoding of 3-valued logic signals using multiple 2-valued signals. --- kernel/calc.cc | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'kernel/calc.cc') diff --git a/kernel/calc.cc b/kernel/calc.cc index 32e8a49fe..9b02a6e30 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -690,5 +690,28 @@ RTLIL::Const RTLIL::const_demux(const RTLIL::Const &arg1, const RTLIL::Const &ar return res; } +RTLIL::Const RTLIL::const_bweqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2) +{ + log_assert(arg2.size() == arg1.size()); + RTLIL::Const result(RTLIL::State::S0, arg1.size()); + for (int i = 0; i < arg1.size(); i++) + result[i] = arg1[i] == arg2[i] ? State::S1 : State::S0; + + return result; +} + +RTLIL::Const RTLIL::const_bwmux(const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3) +{ + log_assert(arg2.size() == arg1.size()); + log_assert(arg3.size() == arg1.size()); + RTLIL::Const result(RTLIL::State::Sx, arg1.size()); + for (int i = 0; i < arg1.size(); i++) { + if (arg3[i] != State::Sx || arg1[i] == arg2[i]) + result[i] = arg3[i] == State::S1 ? arg2[i] : arg1[i]; + } + + return result; +} + YOSYS_NAMESPACE_END -- cgit v1.2.3