From 7191dd16f9d486fbe107b2c24d1858c8f88329b3 Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 18 Jun 2020 23:34:52 +0000 Subject: Use C++11 final/override keywords. --- kernel/celledges.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'kernel/celledges.h') diff --git a/kernel/celledges.h b/kernel/celledges.h index 2cc297cb2..d105e4009 100644 --- a/kernel/celledges.h +++ b/kernel/celledges.h @@ -38,7 +38,7 @@ struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase dict> db; FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { } - void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE { + void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override { SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]); SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]); db[from_sigbit].insert(to_sigbit); @@ -51,7 +51,7 @@ struct RevCellEdgesDatabase : AbstractCellEdgesDatabase dict> db; RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { } - void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE { + void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override { SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]); SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]); db[to_sigbit].insert(from_sigbit); -- cgit v1.2.3