From ff9713dd86cb6390f30392580e665095055a867c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Sat, 22 May 2021 16:48:46 +0200
Subject: kernel/mem: Add model for wide ports.

Such ports cannot actually be created or used yet, this just adds the
necessary plumbing in the helper.  Subsequent commits will gradually
add wide port support to various yosys passes.
---
 kernel/mem.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'kernel/mem.h')

diff --git a/kernel/mem.h b/kernel/mem.h
index af06e970a..e0d8c277f 100644
--- a/kernel/mem.h
+++ b/kernel/mem.h
@@ -29,6 +29,7 @@ struct MemRd {
 	bool removed;
 	dict<IdString, Const> attributes;
 	Cell *cell;
+	int wide_log2;
 	bool clk_enable, clk_polarity;
 	bool transparent;
 	SigSpec clk, en, addr, data;
@@ -39,6 +40,7 @@ struct MemWr {
 	bool removed;
 	dict<IdString, Const> attributes;
 	Cell *cell;
+	int wide_log2;
 	bool clk_enable, clk_polarity;
 	std::vector<bool> priority_mask;
 	SigSpec clk, en, addr, data;
-- 
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