From b54972c1120fa6c5f4dc85d58178fb1211547691 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 25 Jan 2017 17:00:59 +0100
Subject: Fix RTLIL::Memory::start_offset initialization

---
 kernel/rtlil.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'kernel/rtlil.cc')

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 40ad8ca13..365bfd9f8 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2050,6 +2050,7 @@ RTLIL::Memory::Memory()
 	hashidx_ = hashidx_count;
 
 	width = 1;
+	start_offset = 0;
 	size = 0;
 }
 
-- 
cgit v1.2.3


From 3928482a3c4fb71b8e6ccdcb362c030eef34a479 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 4 Feb 2017 14:14:26 +0100
Subject: Add $cover cell type and SVA cover() support

---
 kernel/rtlil.cc | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

(limited to 'kernel/rtlil.cc')

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 365bfd9f8..978a7a537 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1026,7 +1026,7 @@ namespace {
 				return;
 			}
 
-			if (cell->type.in("$assert", "$assume")) {
+			if (cell->type.in("$assert", "$assume", "$cover")) {
 				port("\\A", 1);
 				port("\\EN", 1);
 				check_expected();
@@ -1819,6 +1819,14 @@ RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a
 	return cell;
 }
 
+RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
+{
+	RTLIL::Cell *cell = addCell(name, "$cover");
+	cell->setPort("\\A", sig_a);
+	cell->setPort("\\EN", sig_en);
+	return cell;
+}
+
 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
 {
 	RTLIL::Cell *cell = addCell(name, "$equiv");
-- 
cgit v1.2.3