From 924d9d6e86a5e9a2294479345daac1c03d78008a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 25 Sep 2015 12:23:11 +0200 Subject: Added read-enable to memory model --- kernel/rtlil.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'kernel/rtlil.cc') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 8ff521952..7090fe913 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -947,6 +947,7 @@ namespace { param_bool("\\CLK_POLARITY"); param_bool("\\TRANSPARENT"); port("\\CLK", 1); + port("\\EN", 1); port("\\ADDR", param("\\ABITS")); port("\\DATA", param("\\WIDTH")); check_expected(); @@ -986,6 +987,7 @@ namespace { param_bits("\\WR_CLK_ENABLE", std::max(1, param("\\WR_PORTS"))); param_bits("\\WR_CLK_POLARITY", std::max(1, param("\\WR_PORTS"))); port("\\RD_CLK", param("\\RD_PORTS")); + port("\\RD_EN", param("\\RD_PORTS")); port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS")); port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH")); port("\\WR_CLK", param("\\WR_PORTS")); -- cgit v1.2.3