From bdc316db50cd8b68ef096386a89c1b38793784e1 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 14 Oct 2016 15:24:03 +0200
Subject: Added $anyseq cell type

---
 kernel/rtlil.cc | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

(limited to 'kernel/rtlil.cc')

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index b0cda67b4..66bbf0427 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1037,7 +1037,7 @@ namespace {
 				return;
 			}
 
-			if (cell->type == "$anyconst") {
+			if (cell->type.in("$anyconst", "$anyseq")) {
 				port("\\Y", param("\\WIDTH"));
 				check_expected();
 				return;
@@ -2009,6 +2009,15 @@ RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width)
 	return sig;
 }
 
+RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width)
+{
+	RTLIL::SigSpec sig = addWire(NEW_ID, width);
+	Cell *cell = addCell(name, "$anyseq");
+	cell->setParam("\\WIDTH", width);
+	cell->setPort("\\Y", sig);
+	return sig;
+}
+
 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name)
 {
 	RTLIL::SigSpec sig = addWire(NEW_ID);
-- 
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