From bf7b73acfc2b5e46206e5688b8a6e8d9b0d60d8f Mon Sep 17 00:00:00 2001
From: Benedikt Tutzer <e1225461@student.tuwien.ac.at>
Date: Mon, 13 Aug 2018 15:18:46 +0200
Subject: Added Wrappers for: -IdString -Const -CaseRule -SwitchRule -SyncRule
 -Process -SigChunk -SigBit -SigSpec With all their member functions as well
 as the remaining member functions for Cell, Wire, Module and Design and
 static functions of rtlil.h

---
 kernel/rtlil.cc | 32 +++++++++++++++++++++++++++++++-
 1 file changed, 31 insertions(+), 1 deletion(-)

(limited to 'kernel/rtlil.cc')

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 6e8b51682..bcda931d2 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -74,6 +74,13 @@ RTLIL::Const::Const(const std::vector<bool> &bits)
 		this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
 }
 
+RTLIL::Const::Const(const RTLIL::Const &c)
+{
+	flags = c.flags;
+	for (auto b : c.bits)
+		this->bits.push_back(b);
+}
+
 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
 {
 	if (bits.size() != other.bits.size())
@@ -2247,6 +2254,9 @@ RTLIL::Memory::Memory()
 	width = 1;
 	start_offset = 0;
 	size = 0;
+#ifdef WITH_PYTHON
+	RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
+#endif
 }
 
 RTLIL::Cell::Cell() : module(nullptr)
@@ -2534,6 +2544,14 @@ RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
 	width = 1;
 }
 
+RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data)
+{
+	wire = sigchunk.wire;
+	data = sigchunk.data;
+	width = sigchunk.width;
+	offset = sigchunk.offset;
+}
+
 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
 {
 	RTLIL::SigChunk ret;
@@ -3907,6 +3925,18 @@ RTLIL::Process *RTLIL::Process::clone() const
 
 	return new_proc;
 }
+RTLIL::Memory::~Memory()
+{
+#ifdef WITH_PYTHON
+	RTLIL::Memory::get_all_memorys()->erase(hashidx_);
+#endif
+}
 
+#ifdef WITH_PYTHON
+static std::map<unsigned int, RTLIL::Memory*> *all_memorys = new std::map<unsigned int, RTLIL::Memory*>();
+std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
+{
+	return all_memorys;
+}
+#endif
 YOSYS_NAMESPACE_END
-
-- 
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