From f483dce7c231f83937b5944ed0166a70594a0e8b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 29 Apr 2015 07:28:15 +0200
Subject: Added $eq/$neq -> $logic_not/$reduce_bool optimization

---
 kernel/rtlil.cc | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

(limited to 'kernel/rtlil.cc')

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 8c0b41d09..bf0fd1c89 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3000,6 +3000,21 @@ bool RTLIL::SigSpec::is_fully_const() const
 	return true;
 }
 
+bool RTLIL::SigSpec::is_fully_zero() const
+{
+	cover("kernel.rtlil.sigspec.is_fully_zero");
+
+	pack();
+	for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
+		if (it->width > 0 && it->wire != NULL)
+			return false;
+		for (size_t i = 0; i < it->data.size(); i++)
+			if (it->data[i] != RTLIL::State::S0)
+				return false;
+	}
+	return true;
+}
+
 bool RTLIL::SigSpec::is_fully_def() const
 {
 	cover("kernel.rtlil.sigspec.is_fully_def");
-- 
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