From b54972c1120fa6c5f4dc85d58178fb1211547691 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 25 Jan 2017 17:00:59 +0100 Subject: Fix RTLIL::Memory::start_offset initialization --- kernel/rtlil.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 40ad8ca13..365bfd9f8 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2050,6 +2050,7 @@ RTLIL::Memory::Memory() hashidx_ = hashidx_count; width = 1; + start_offset = 0; size = 0; } -- cgit v1.2.3 From 3928482a3c4fb71b8e6ccdcb362c030eef34a479 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 4 Feb 2017 14:14:26 +0100 Subject: Add $cover cell type and SVA cover() support --- kernel/celltypes.h | 1 + kernel/rtlil.cc | 10 +++++++++- kernel/rtlil.h | 1 + 3 files changed, 11 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index f0ead1e89..04db5125e 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -116,6 +116,7 @@ struct CellTypes setup_type("$assert", {A, EN}, pool(), true); setup_type("$assume", {A, EN}, pool(), true); + setup_type("$cover", {A, EN}, pool(), true); setup_type("$initstate", pool(), {Y}, true); setup_type("$anyconst", pool(), {Y}, true); setup_type("$anyseq", pool(), {Y}, true); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 365bfd9f8..978a7a537 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1026,7 +1026,7 @@ namespace { return; } - if (cell->type.in("$assert", "$assume")) { + if (cell->type.in("$assert", "$assume", "$cover")) { port("\\A", 1); port("\\EN", 1); check_expected(); @@ -1819,6 +1819,14 @@ RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a return cell; } +RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en) +{ + RTLIL::Cell *cell = addCell(name, "$cover"); + cell->setPort("\\A", sig_a); + cell->setPort("\\EN", sig_en); + return cell; +} + RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y) { RTLIL::Cell *cell = addCell(name, "$equiv"); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 8dd8fcca3..7a6f5717d 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1007,6 +1007,7 @@ public: RTLIL::Cell* addTribuf (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y); RTLIL::Cell* addAssert (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en); RTLIL::Cell* addAssume (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en); + RTLIL::Cell* addCover (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en); RTLIL::Cell* addEquiv (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y); RTLIL::Cell* addSr (RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true); -- cgit v1.2.3 From aab58045a867a6a7d2998d329a9f20924ab7b8a1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 5 Feb 2017 22:43:33 +0100 Subject: Fix undef propagation bug in $pmux SAT model --- kernel/satgen.h | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) (limited to 'kernel') diff --git a/kernel/satgen.h b/kernel/satgen.h index 690f8e337..25a22fd8a 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -507,11 +507,7 @@ struct SatGen std::vector undef_s = importUndefSigSpec(cell->getPort("\\S"), timestep); std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); - int maybe_one_hot = ez->CONST_FALSE; - int maybe_many_hot = ez->CONST_FALSE; - - int sure_one_hot = ez->CONST_FALSE; - int sure_many_hot = ez->CONST_FALSE; + int maybe_a = ez->CONST_TRUE; std::vector bits_set = std::vector(undef_y.size(), ez->CONST_FALSE); std::vector bits_clr = std::vector(undef_y.size(), ez->CONST_FALSE); @@ -524,18 +520,12 @@ struct SatGen int maybe_s = ez->OR(s.at(i), undef_s.at(i)); int sure_s = ez->AND(s.at(i), ez->NOT(undef_s.at(i))); - maybe_one_hot = ez->OR(maybe_one_hot, maybe_s); - maybe_many_hot = ez->OR(maybe_many_hot, ez->AND(maybe_one_hot, maybe_s)); - - sure_one_hot = ez->OR(sure_one_hot, sure_s); - sure_many_hot = ez->OR(sure_many_hot, ez->AND(sure_one_hot, sure_s)); + maybe_a = ez->AND(maybe_a, ez->NOT(sure_s)); - bits_set = ez->vec_ite(maybe_s, ez->vec_or(bits_set, ez->vec_or(bits_set, ez->vec_or(part_of_b, part_of_undef_b))), bits_set); - bits_clr = ez->vec_ite(maybe_s, ez->vec_or(bits_clr, ez->vec_or(bits_clr, ez->vec_or(ez->vec_not(part_of_b), part_of_undef_b))), bits_clr); + bits_set = ez->vec_ite(maybe_s, ez->vec_or(bits_set, ez->vec_or(part_of_b, part_of_undef_b)), bits_set); + bits_clr = ez->vec_ite(maybe_s, ez->vec_or(bits_clr, ez->vec_or(ez->vec_not(part_of_b), part_of_undef_b)), bits_clr); } - int maybe_a = ez->NOT(maybe_one_hot); - bits_set = ez->vec_ite(maybe_a, ez->vec_or(bits_set, ez->vec_or(bits_set, ez->vec_or(a, undef_a))), bits_set); bits_clr = ez->vec_ite(maybe_a, ez->vec_or(bits_clr, ez->vec_or(bits_clr, ez->vec_or(ez->vec_not(a), undef_a))), bits_clr); -- cgit v1.2.3