From 3cc95fb4be27a3e130563db102ed268876027288 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 21 Apr 2019 21:58:57 +0200 Subject: Add specify parser Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7e1159cac..7d5334eb1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1194,6 +1194,16 @@ namespace { return; } + if (cell->type == "$specify2") { + // FIXME + return; + } + + if (cell->type == "$specify3") { + // FIXME + return; + } + if (cell->type == "$_BUF_") { check_gate("AY"); return; } if (cell->type == "$_NOT_") { check_gate("AY"); return; } if (cell->type == "$_AND_") { check_gate("ABY"); return; } -- cgit v1.2.3 From e1d73e03d38e9408cc7bce685645bb170ca5a6b8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 22 Apr 2019 09:26:20 +0200 Subject: Add InternalCellChecker support for $specify2 and $specify3 Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7d5334eb1..9e06b8323 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1194,13 +1194,27 @@ namespace { return; } - if (cell->type == "$specify2") { - // FIXME - return; - } - - if (cell->type == "$specify3") { - // FIXME + if (cell->type.in("$specify2", "$specify3")) { + param_bool("\\FULL"); + param_bool("\\SRC_DST_PEN"); + param_bool("\\SRC_DST_POL"); + param("\\T_RISE_MIN"); + param("\\T_RISE_AVG"); + param("\\T_RISE_MAX"); + param("\\T_FALL_MIN"); + param("\\T_FALL_AVG"); + param("\\T_FALL_MAX"); + port("\\EN", 1); + port("\\SRC", param("\\SRC_WIDTH")); + port("\\DST", param("\\DST_WIDTH")); + if (cell->type == "$specify3") { + param_bool("\\EDGE_EN"); + param_bool("\\EDGE_POL"); + param_bool("\\DAT_DST_PEN"); + param_bool("\\DAT_DST_POL"); + port("\\DAT", param("\\DST_WIDTH")); + } + check_expected(); return; } -- cgit v1.2.3 From aec2475a9d7a2a903d5015840a3320ce2cedf5cd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 22 Apr 2019 09:29:59 +0200 Subject: Add CellTypes support for $specify2 and $specify3 Signed-off-by: Clifford Wolf --- kernel/celltypes.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 0da78c313..f8c73ed83 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -85,6 +85,7 @@ struct CellTypes setup_internals_eval(); IdString A = "\\A", B = "\\B", EN = "\\EN", Y = "\\Y"; + IdString SRC = "\\SRC", DST = "\\DST", DAT = "\\DAT"; setup_type("$tribuf", {A, EN}, {Y}, true); @@ -99,6 +100,8 @@ struct CellTypes setup_type("$allconst", pool(), {Y}, true); setup_type("$allseq", pool(), {Y}, true); setup_type("$equiv", {A, B}, {Y}, true); + setup_type("$specify2", {EN, SRC, DST}, pool(), true); + setup_type("$specify3", {EN, SRC, DST, DAT}, pool(), true); } void setup_internals_eval() -- cgit v1.2.3 From e807e88b607834170692f56a5538b89fd4175a36 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 22 Apr 2019 09:52:47 +0200 Subject: Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 9e06b8323..4522b0a08 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1199,10 +1199,10 @@ namespace { param_bool("\\SRC_DST_PEN"); param_bool("\\SRC_DST_POL"); param("\\T_RISE_MIN"); - param("\\T_RISE_AVG"); + param("\\T_RISE_TYP"); param("\\T_RISE_MAX"); param("\\T_FALL_MIN"); - param("\\T_FALL_AVG"); + param("\\T_FALL_TYP"); param("\\T_FALL_MAX"); port("\\EN", 1); port("\\SRC", param("\\SRC_WIDTH")); -- cgit v1.2.3 From 71c38d9de527e1a8b55ba295df459fbcf2a0fe47 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 23 Apr 2019 15:46:40 +0200 Subject: Add $specrule cells for $setup/$hold/$skew specify rules Signed-off-by: Clifford Wolf --- kernel/celltypes.h | 2 ++ kernel/rtlil.cc | 15 +++++++++++++++ 2 files changed, 17 insertions(+) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index f8c73ed83..4e91eddda 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -86,6 +86,7 @@ struct CellTypes IdString A = "\\A", B = "\\B", EN = "\\EN", Y = "\\Y"; IdString SRC = "\\SRC", DST = "\\DST", DAT = "\\DAT"; + IdString EN_SRC = "\\EN_SRC", EN_DST = "\\EN_DST"; setup_type("$tribuf", {A, EN}, {Y}, true); @@ -102,6 +103,7 @@ struct CellTypes setup_type("$equiv", {A, B}, {Y}, true); setup_type("$specify2", {EN, SRC, DST}, pool(), true); setup_type("$specify3", {EN, SRC, DST, DAT}, pool(), true); + setup_type("$specrule", {EN_SRC, EN_DST, SRC, DST}, pool(), true); } void setup_internals_eval() diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 4522b0a08..dae3698a9 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1218,6 +1218,21 @@ namespace { return; } + if (cell->type == "$specrule") { + param_bool("\\SRC_PEN"); + param_bool("\\SRC_POL"); + param_bool("\\DST_PEN"); + param_bool("\\DST_POL"); + param_bool("\\LIMIT_GT"); + param("\\T_LIMIT"); + port("\\SRC_EN", 1); + port("\\DST_EN", 1); + port("\\SRC", param("\\SRC_WIDTH")); + port("\\DST", param("\\DST_WIDTH")); + check_expected(); + return; + } + if (cell->type == "$_BUF_") { check_gate("AY"); return; } if (cell->type == "$_NOT_") { check_gate("AY"); return; } if (cell->type == "$_AND_") { check_gate("ABY"); return; } -- cgit v1.2.3 From 4575e4ad86494e99dd05200f7242dfa632053c78 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 23 Apr 2019 22:18:04 +0200 Subject: Improve $specrule interface Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index dae3698a9..3dd18c296 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1223,7 +1223,8 @@ namespace { param_bool("\\SRC_POL"); param_bool("\\DST_PEN"); param_bool("\\DST_POL"); - param_bool("\\LIMIT_GT"); + param_bool("\\SKEW"); + param_bool("\\HOLD"); param("\\T_LIMIT"); port("\\SRC_EN", 1); port("\\DST_EN", 1); -- cgit v1.2.3 From 64925b4e8f7890f5447d9655b2c69dd59a93f7cd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 23 Apr 2019 22:57:10 +0200 Subject: Improve $specrule interface Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 3dd18c296..040644c47 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1219,13 +1219,13 @@ namespace { } if (cell->type == "$specrule") { + param("\\TYPE"); param_bool("\\SRC_PEN"); param_bool("\\SRC_POL"); param_bool("\\DST_PEN"); param_bool("\\DST_POL"); - param_bool("\\SKEW"); - param_bool("\\HOLD"); param("\\T_LIMIT"); + param("\\T_LIMIT2"); port("\\SRC_EN", 1); port("\\DST_EN", 1); port("\\SRC", param("\\SRC_WIDTH")); -- cgit v1.2.3 From 87426f5a06b0cf9d1fe44efda65e3c048d89d322 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 4 May 2019 08:46:24 +0200 Subject: Improve write_verilog specify support Signed-off-by: Clifford Wolf --- kernel/rtlil.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index db5c33c73..0c3fa6f76 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -50,7 +50,7 @@ namespace RTLIL CONST_FLAG_NONE = 0, CONST_FLAG_STRING = 1, CONST_FLAG_SIGNED = 2, // only used for parameters - CONST_FLAG_REAL = 4 // unused -- to be used for parameters + CONST_FLAG_REAL = 4 // only used for parameters }; struct Const; -- cgit v1.2.3 From bafbb9ee905f042056d723ecde4a62d58b6d8f4c Mon Sep 17 00:00:00 2001 From: Matthew Daiter Date: Mon, 6 May 2019 18:33:56 -0500 Subject: Optimize ceil_log2 function --- kernel/yosys.cc | 6 ++++-- kernel/yosys.h | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 20d972150..377572fc2 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -151,14 +151,16 @@ void yosys_banner() int ceil_log2(int x) { +#if defined(__GNUC__) + return x > 1 ? (8*sizeof(int)) - __builtin_clz(x-1) : 0; +#else if (x <= 0) return 0; - for (int i = 0; i < 32; i++) if (((x-1) >> i) == 0) return i; - log_abort(); +#endif } std::string stringf(const char *fmt, ...) diff --git a/kernel/yosys.h b/kernel/yosys.h index 82eb069ab..c7b671724 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -244,7 +244,7 @@ extern bool memhasher_active; inline void memhasher() { if (memhasher_active) memhasher_do(); } void yosys_banner(); -int ceil_log2(int x); +int ceil_log2(int x) YS_ATTRIBUTE(const); std::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2)); std::string vstringf(const char *fmt, va_list ap); int readsome(std::istream &f, char *s, int n); -- cgit v1.2.3 From 6e629d289515e2792fa644fca105998bd9e366de Mon Sep 17 00:00:00 2001 From: Matthew Daiter Date: Tue, 7 May 2019 22:04:28 -0500 Subject: Minor optimization to get_attribute_bool --- kernel/rtlil.cc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 147d378e5..79ff4a6a6 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -218,15 +218,19 @@ void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value) { if (value) attributes[id] = RTLIL::Const(1); - else if (attributes.count(id)) - attributes.erase(id); + else { + const auto it = attributes.find(id); + if (it != attributes.end()) + attributes.erase(it); + } } bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const { - if (attributes.count(id) == 0) + const auto it = attributes.find(id); + if (it == attributes.end()) return false; - return attributes.at(id).as_bool(); + return it->second.as_bool(); } void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool &data) -- cgit v1.2.3 From 30c762d3a148afa9e27a93c1fa098b7c478511a4 Mon Sep 17 00:00:00 2001 From: Kristoffer Ellersgaard Koch Date: Sun, 5 May 2019 10:00:27 +0200 Subject: Fix all warnings that occurred when compiling with gcc9 --- kernel/rtlil.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index db5c33c73..54c8ee3bd 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -518,6 +518,7 @@ struct RTLIL::Const Const(const std::vector &bits) : bits(bits) { flags = CONST_FLAG_NONE; } Const(const std::vector &bits); Const(const RTLIL::Const &c); + RTLIL::Const &operator =(const RTLIL::Const &other) = default; bool operator <(const RTLIL::Const &other) const; bool operator ==(const RTLIL::Const &other) const; @@ -597,6 +598,7 @@ struct RTLIL::SigChunk SigChunk(RTLIL::State bit, int width = 1); SigChunk(RTLIL::SigBit bit); SigChunk(const RTLIL::SigChunk &sigchunk); + RTLIL::SigChunk &operator =(const RTLIL::SigChunk &other) = default; RTLIL::SigChunk extract(int offset, int length) const; @@ -622,6 +624,7 @@ struct RTLIL::SigBit SigBit(const RTLIL::SigChunk &chunk, int index); SigBit(const RTLIL::SigSpec &sig); SigBit(const RTLIL::SigBit &sigbit); + RTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default; bool operator <(const RTLIL::SigBit &other) const; bool operator ==(const RTLIL::SigBit &other) const; -- cgit v1.2.3 From 287de4b848bdd33a9ba52018fc9b9779a10e60c7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 15 May 2019 16:01:00 +0200 Subject: Add rewrite_sigspecs2, Improve remove() wires Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 29 +++++++++++++++++++++------- kernel/rtlil.h | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+), 7 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 79ff4a6a6..790ba52a3 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1514,7 +1514,10 @@ void RTLIL::Module::add(RTLIL::Cell *cell) cell->module = this; } -namespace { +void RTLIL::Module::remove(const pool &wires) +{ + log_assert(refcount_wires_ == 0); + struct DeleteWireWorker { RTLIL::Module *module; @@ -1529,17 +1532,29 @@ namespace { } sig = chunks; } - }; -} -void RTLIL::Module::remove(const pool &wires) -{ - log_assert(refcount_wires_ == 0); + void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) { + log_assert(GetSize(lhs) == GetSize(rhs)); + RTLIL::SigSpec new_lhs, new_rhs; + for (int i = 0; i < GetSize(lhs); i++) { + RTLIL::SigBit lhs_bit = lhs[i]; + if (lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) + continue; + RTLIL::SigBit rhs_bit = rhs[i]; + if (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire)) + continue; + new_lhs.append(lhs_bit); + new_rhs.append(rhs_bit); + } + lhs = new_lhs; + rhs = new_rhs; + } + }; DeleteWireWorker delete_wire_worker; delete_wire_worker.module = this; delete_wire_worker.wires_p = &wires; - rewrite_sigspecs(delete_wire_worker); + rewrite_sigspecs2(delete_wire_worker); for (auto &it : wires) { log_assert(wires_.count(it->name) != 0); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index a0270bd1c..81ca93dce 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1001,6 +1001,7 @@ public: void fixup_ports(); template void rewrite_sigspecs(T &functor); + template void rewrite_sigspecs2(T &functor); void cloneInto(RTLIL::Module *new_mod) const; virtual RTLIL::Module *clone() const; @@ -1306,6 +1307,7 @@ public: } template void rewrite_sigspecs(T &functor); + template void rewrite_sigspecs2(T &functor); #ifdef WITH_PYTHON static std::map *get_all_cells(void); @@ -1324,6 +1326,7 @@ struct RTLIL::CaseRule bool empty() const; template void rewrite_sigspecs(T &functor); + template void rewrite_sigspecs2(T &functor); RTLIL::CaseRule *clone() const; }; @@ -1337,6 +1340,7 @@ struct RTLIL::SwitchRule : public RTLIL::AttrObject bool empty() const; template void rewrite_sigspecs(T &functor); + template void rewrite_sigspecs2(T &functor); RTLIL::SwitchRule *clone() const; }; @@ -1347,6 +1351,7 @@ struct RTLIL::SyncRule std::vector actions; template void rewrite_sigspecs(T &functor); + template void rewrite_sigspecs2(T &functor); RTLIL::SyncRule *clone() const; }; @@ -1359,6 +1364,7 @@ struct RTLIL::Process : public RTLIL::AttrObject ~Process(); template void rewrite_sigspecs(T &functor); + template void rewrite_sigspecs2(T &functor); RTLIL::Process *clone() const; }; @@ -1420,12 +1426,30 @@ void RTLIL::Module::rewrite_sigspecs(T &functor) } } +template +void RTLIL::Module::rewrite_sigspecs2(T &functor) +{ + for (auto &it : cells_) + it.second->rewrite_sigspecs2(functor); + for (auto &it : processes) + it.second->rewrite_sigspecs2(functor); + for (auto &it : connections_) { + functor(it.first, it.second); + } +} + template void RTLIL::Cell::rewrite_sigspecs(T &functor) { for (auto &it : connections_) functor(it.second); } +template +void RTLIL::Cell::rewrite_sigspecs2(T &functor) { + for (auto &it : connections_) + functor(it.second); +} + template void RTLIL::CaseRule::rewrite_sigspecs(T &functor) { for (auto &it : compare) @@ -1438,6 +1462,17 @@ void RTLIL::CaseRule::rewrite_sigspecs(T &functor) { it->rewrite_sigspecs(functor); } +template +void RTLIL::CaseRule::rewrite_sigspecs2(T &functor) { + for (auto &it : compare) + functor(it); + for (auto &it : actions) { + functor(it.first, it.second); + } + for (auto it : switches) + it->rewrite_sigspecs2(functor); +} + template void RTLIL::SwitchRule::rewrite_sigspecs(T &functor) { @@ -1446,6 +1481,14 @@ void RTLIL::SwitchRule::rewrite_sigspecs(T &functor) it->rewrite_sigspecs(functor); } +template +void RTLIL::SwitchRule::rewrite_sigspecs2(T &functor) +{ + functor(signal); + for (auto it : cases) + it->rewrite_sigspecs2(functor); +} + template void RTLIL::SyncRule::rewrite_sigspecs(T &functor) { @@ -1456,6 +1499,15 @@ void RTLIL::SyncRule::rewrite_sigspecs(T &functor) } } +template +void RTLIL::SyncRule::rewrite_sigspecs2(T &functor) +{ + functor(signal); + for (auto &it : actions) { + functor(it.first, it.second); + } +} + template void RTLIL::Process::rewrite_sigspecs(T &functor) { @@ -1464,6 +1516,14 @@ void RTLIL::Process::rewrite_sigspecs(T &functor) it->rewrite_sigspecs(functor); } +template +void RTLIL::Process::rewrite_sigspecs2(T &functor) +{ + root_case.rewrite_sigspecs2(functor); + for (auto it : syncs) + it->rewrite_sigspecs2(functor); +} + YOSYS_NAMESPACE_END #endif -- cgit v1.2.3