From 2cb47355d4b3e8021a88f68f7a5f33ce46ff51b0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 28 Jan 2014 06:55:47 +0100 Subject: Renamed manual/FILES_* directories --- manual/CHAPTER_Eval/openmsp430.prj | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 manual/CHAPTER_Eval/openmsp430.prj (limited to 'manual/CHAPTER_Eval/openmsp430.prj') diff --git a/manual/CHAPTER_Eval/openmsp430.prj b/manual/CHAPTER_Eval/openmsp430.prj new file mode 100644 index 000000000..cb8cd2714 --- /dev/null +++ b/manual/CHAPTER_Eval/openmsp430.prj @@ -0,0 +1,14 @@ +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sync_cell.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sync_reset.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_register_file.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_dbg_uart.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_alu.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_watchdog.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sfr.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_multiplier.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_mem_backbone.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_frontend.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_execution_unit.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_dbg.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_clock_module.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/openMSP430.v" -- cgit v1.2.3