From 4e03865d5bf3fafe0bd3735c88431675d53d2663 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= Date: Tue, 23 Feb 2021 00:21:46 +0100 Subject: Add support for memory writes in processes. --- manual/CHAPTER_Overview.tex | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'manual/CHAPTER_Overview.tex') diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index 83db5aac7..50a56137c 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -350,8 +350,9 @@ to update {\tt \textbackslash{}q}. An RTLIL::Process is a container for zero or more RTLIL::SyncRule objects and exactly one RTLIL::CaseRule object, which is called the {\it root case}. -An RTLIL::SyncRule object contains an (optional) synchronization condition (signal and edge-type) and zero or -more assignments (RTLIL::SigSig). The {\tt always} synchronization condition is used to break combinatorial +An RTLIL::SyncRule object contains an (optional) synchronization condition (signal and edge-type), zero or +more assignments (RTLIL::SigSig), and zero or more memory writes (RTLIL::MemWriteAction). +The {\tt always} synchronization condition is used to break combinatorial loops when a latch should be inferred instead. An RTLIL::CaseRule is a container for zero or more assignments (RTLIL::SigSig) -- cgit v1.2.3