From f9946232adf887e5aa4a48c64f88eaa17e424009 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:49:51 +0200 Subject: Refactoring: Renamed RTLIL::Module::wires to wires_ --- manual/CHAPTER_Prog/stubnets.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'manual/CHAPTER_Prog') diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index f67ffe1e8..9eacfbcb5 100644 --- a/manual/CHAPTER_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc @@ -43,7 +43,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re } // for each wire in the module - for (auto &wire_iter : module->wires) + for (auto &wire_iter : module->wires_) { RTLIL::Wire *wire = wire_iter.second; -- cgit v1.2.3