From 34b39ec28a81818cda0a77c448819ecbf9da3cce Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 29 Jan 2014 15:56:58 +0100 Subject: presentation progress --- manual/PRESENTATION_Intro/counter.ys | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'manual/PRESENTATION_Intro') diff --git a/manual/PRESENTATION_Intro/counter.ys b/manual/PRESENTATION_Intro/counter.ys index 68fe0308e..bcfe387e4 100644 --- a/manual/PRESENTATION_Intro/counter.ys +++ b/manual/PRESENTATION_Intro/counter.ys @@ -2,17 +2,17 @@ read_verilog counter.v hierarchy -check -top counter -show -format pdf -prefix counter_00 +show -stretch -format pdf -prefix counter_00 # the high-level stuff proc; opt; memory; opt; fsm; opt -show -format pdf -prefix counter_01 +show -stretch -format pdf -prefix counter_01 # mapping to internal cell library techmap; splitnets -ports; opt -show -format pdf -prefix counter_02 +show -stretch -format pdf -prefix counter_02 # mapping flip-flops to mycells.lib dfflibmap -liberty mycells.lib @@ -23,4 +23,4 @@ abc -liberty mycells.lib # cleanup clean -show -lib mycells.v -format pdf -prefix counter_03 +show -stretch -lib mycells.v -format pdf -prefix counter_03 -- cgit v1.2.3