From 1184a7f3b41f9044b603406c914bf43ab1808b28 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= Date: Wed, 8 Dec 2021 23:23:03 +0100 Subject: opt_mem_priority: Fix non-ascii char in help message. This is a fixed version of #3072. --- manual/command-reference-manual.tex | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) (limited to 'manual/command-reference-manual.tex') diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index d9a2f8dc1..28d2b6107 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -3163,7 +3163,7 @@ for removal of the read port. opt_mem_priority [selection] This pass detects cases where one memory write port has priority over another -even though they can never collide with each other — ie. there can never be +even though they can never collide with each other -- ie. there can never be a situation where a given memory bit is written by both ports at the same time, for example because of always-different addresses, or mutually exclusive enable signals. In such cases, the priority relation is removed. @@ -3661,11 +3661,6 @@ Additional -D[=] options may be added after the option indicating the language version (and before file names) to set additional verilog defines. - read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} .. - -Load the specified VHDL files. (Requires Verific.) - - read {-f|-F} Load and execute the specified command file. (Requires Verific.) @@ -7480,11 +7475,6 @@ The macros SYNTHESIS and VERIFIC are defined implicitly. Like -sv, but define FORMAL instead of SYNTHESIS. - verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} .. - -Load the specified VHDL files into Verific. - - verific {-f|-F} Load and execute the specified command file. -- cgit v1.2.3