From cb17eeaf5008a87384b3888dc34993928daba918 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 3 Jan 2022 11:57:11 +0100
Subject: Update manual

---
 manual/command-reference-manual.tex | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

(limited to 'manual/command-reference-manual.tex')

diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index 28d2b6107..2d5f55749 100644
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -871,6 +871,16 @@ When commands are separated using the ';;;' token, this command will be executed
 in -purge mode between the commands.
 \end{lstlisting}
 
+\section{clean\_zerowidth -- clean zero-width connections from the design}
+\label{cmd:clean_zerowidth}
+\begin{lstlisting}[numbers=left,frame=single]
+    clean_zerowidth [selection]
+
+Fixes the selected cells and processes to contain no zero-width connections.
+Depending on the cell type, this may be implemented by removing the connection,
+widening it to 1-bit, or removing the cell altogether.
+\end{lstlisting}
+
 \section{clk2fflogic -- convert clocked FFs to generic \$ff cells}
 \label{cmd:clk2fflogic}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -3661,6 +3671,11 @@ Additional -D<macro>[=<value>] options may be added after the option indicating
 the language version (and before file names) to set additional verilog defines.
 
 
+    read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..
+
+Load the specified VHDL files. (Requires Verific.)
+
+
     read {-f|-F} <command-file>
 
 Load and execute the specified command file. (Requires Verific.)
@@ -7467,7 +7482,7 @@ different compilation units.
 
 Additional -D<macro>[=<value>] options may be added after the option indicating
 the language version (and before file names) to set additional verilog defines.
-The macros SYNTHESIS and VERIFIC are defined implicitly.
+The macros YOSYS, SYNTHESIS, and VERIFIC are defined implicitly.
 
 
     verific -formal <verilog-file>..
@@ -7475,6 +7490,11 @@ The macros SYNTHESIS and VERIFIC are defined implicitly.
 Like -sv, but define FORMAL instead of SYNTHESIS.
 
 
+    verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..
+
+Load the specified VHDL files into Verific.
+
+
     verific {-f|-F} <command-file>
 
 Load and execute the specified command file.
-- 
cgit v1.2.3

