From 1bf7a18fec76cf46a5b8710a75371e23b68d147d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 14 Aug 2014 16:13:42 +0200
Subject: Added module->ports

---
 passes/hierarchy/hierarchy.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'passes/hierarchy/hierarchy.cc')

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 50b4989df..2f28afb25 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -126,6 +126,8 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 			wire->port_output = decl.output;
 		}
 
+		mod->fixup_ports();
+
 		for (auto &para : parameters)
 			log("  ignoring parameter %s.\n", RTLIL::id2cstr(para));
 
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