From 295e352ba6aa1bd71431abc21a8f93735968cae6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 22 Nov 2013 15:01:12 +0100 Subject: Renamed "placeholder" to "blackbox" --- passes/hierarchy/hierarchy.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'passes/hierarchy/hierarchy.cc') diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 7291aa80c..b98afcc1c 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -113,7 +113,7 @@ static void generate(RTLIL::Design *design, const std::vector &cell RTLIL::Module *mod = new RTLIL::Module; mod->name = celltype; - mod->attributes["\\placeholder"] = RTLIL::Const(1); + mod->attributes["\\blackbox"] = RTLIL::Const(1); design->modules[mod->name] = mod; for (auto &decl : ports) { @@ -147,7 +147,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla } if (cell->parameters.size() == 0) continue; - if (design->modules.at(cell->type)->get_bool_attribute("\\placeholder")) + if (design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) continue; RTLIL::Module *mod = design->modules[cell->type]; cell->type = mod->derive(design, cell->parameters); @@ -280,7 +280,7 @@ struct HierarchyPass : public Pass { log(" use the specified top module to built a design hierarchy. modules\n"); log(" outside this tree (unused modules) are removed.\n"); log("\n"); - log("In -generate mode this pass generates placeholder modules for the given cell\n"); + log("In -generate mode this pass generates blackbox modules for the given cell\n"); log("types (wildcards supported). For this the design is searched for cells that\n"); log("match the given types and then the given port declarations are used to\n"); log("determine the direction of the ports. The syntax for a port declaration is:\n"); -- cgit v1.2.3