From 7bd2d1064f2eceddc3c93c121c4154a2f594a040 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 28 Jul 2014 11:08:55 +0200
Subject: Using log_assert() instead of assert()

---
 passes/hierarchy/hierarchy.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'passes/hierarchy/hierarchy.cc')

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 8aec25eba..c869ec729 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -98,7 +98,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 					generate_port_decl_t d = decl;
 					d.portname = portname;
 					d.index = *indices.begin();
-					assert(!indices.empty());
+					log_assert(!indices.empty());
 					indices.erase(d.index);
 					ports[d.index-1] = d;
 					portwidths[d.portname] = std::max(portwidths[d.portname], 1);
@@ -110,7 +110,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 			portnames.erase(portname);
 		}
 
-		assert(indices.empty());
+		log_assert(indices.empty());
 
 		RTLIL::Module *mod = new RTLIL::Module;
 		mod->name = celltype;
-- 
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