From 0d8e5d965f2585e6ed151a9e92d83ee63df6172a Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Fri, 18 Dec 2020 12:59:08 -0700 Subject: Sign extend port connections where necessary - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265 --- passes/hierarchy/hierarchy.cc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'passes/hierarchy/hierarchy.cc') diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 225e1feae..3372687e1 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -1233,14 +1233,18 @@ struct HierarchyPass : public Pass { { int n = GetSize(conn.second) - GetSize(w); if (!w->port_input && w->port_output) - module->connect(sig.extract(GetSize(w), n), Const(0, n)); + { + RTLIL::SigSpec out = sig.extract(0, GetSize(w)); + out.extend_u0(GetSize(sig), w->is_signed); + module->connect(sig.extract(GetSize(w), n), out.extract(GetSize(w), n)); + } sig.remove(GetSize(w), n); } else { int n = GetSize(w) - GetSize(conn.second); if (w->port_input && !w->port_output) - sig.append(Const(0, n)); + sig.extend_u0(GetSize(w), sig.is_wire() && sig.as_wire()->is_signed); else sig.append(module->addWire(NEW_ID, n)); } -- cgit v1.2.3