From e6d33513a5b809facc6e3e5e75d2248bfa94f82b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 31 Jul 2014 14:11:39 +0200
Subject: Added module->design and cell->module, wire->module pointers

---
 passes/hierarchy/hierarchy.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/hierarchy/hierarchy.cc')

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index a1361c680..67b57a94d 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -117,7 +117,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 		RTLIL::Module *mod = new RTLIL::Module;
 		mod->name = celltype;
 		mod->attributes["\\blackbox"] = RTLIL::Const(1);
-		design->modules_[mod->name] = mod;
+		design->add(mod);
 
 		for (auto &decl : ports) {
 			RTLIL::Wire *wire = mod->addWire(decl.portname, portwidths.at(decl.portname));
-- 
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