From b7dda723022ad00c6c0089be888eab319953faa8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 14:32:50 +0200 Subject: Changed users of cell->connections_ to the new API (sed command) git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' --- passes/hierarchy/submod.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'passes/hierarchy/submod.cc') diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index df5fd8e37..d72ebb127 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -79,11 +79,11 @@ struct SubmodWorker wire_flags.clear(); for (RTLIL::Cell *cell : submod.cells) { if (ct.cell_known(cell->type)) { - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false); } else { log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str()); - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) flag_signal(conn.second, true, true, true, false, false); } } @@ -92,11 +92,11 @@ struct SubmodWorker if (submod.cells.count(cell) > 0) continue; if (ct.cell_known(cell->type)) { - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) flag_signal(conn.second, false, false, false, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first)); } else { flag_found_something = false; - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) flag_signal(conn.second, false, false, false, true, true); if (flag_found_something) log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str()); @@ -163,7 +163,7 @@ struct SubmodWorker for (RTLIL::Cell *cell : submod.cells) { RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell); - for (auto &conn : new_cell->connections_) + for (auto &conn : new_cell->connections()) for (auto &bit : conn.second) if (bit.wire != NULL) { assert(wire_flags.count(bit.wire) > 0); @@ -180,7 +180,7 @@ struct SubmodWorker RTLIL::Wire *old_wire = it.first; RTLIL::Wire *new_wire = it.second.new_wire; if (new_wire->port_id > 0) - new_cell->connections_[new_wire->name] = RTLIL::SigSpec(old_wire); + new_cell->connections()[new_wire->name] = RTLIL::SigSpec(old_wire); } } -- cgit v1.2.3 From f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 15:57:57 +0200 Subject: Manual fixes for new cell connections API --- passes/hierarchy/submod.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'passes/hierarchy/submod.cc') diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index d72ebb127..ef4a9f16d 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -65,7 +65,7 @@ struct SubmodWorker flag_found_something = true; } - void flag_signal(RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used) + void flag_signal(const RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used) { for (auto &c : sig.chunks()) if (c.wire != NULL) @@ -163,7 +163,7 @@ struct SubmodWorker for (RTLIL::Cell *cell : submod.cells) { RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell); - for (auto &conn : new_cell->connections()) + for (auto &conn : new_cell->connections_) for (auto &bit : conn.second) if (bit.wire != NULL) { assert(wire_flags.count(bit.wire) > 0); @@ -180,7 +180,7 @@ struct SubmodWorker RTLIL::Wire *old_wire = it.first; RTLIL::Wire *new_wire = it.second.new_wire; if (new_wire->port_id > 0) - new_cell->connections()[new_wire->name] = RTLIL::SigSpec(old_wire); + new_cell->set(new_wire->name, RTLIL::SigSpec(old_wire)); } } -- cgit v1.2.3