From e6d33513a5b809facc6e3e5e75d2248bfa94f82b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 31 Jul 2014 14:11:39 +0200
Subject: Added module->design and cell->module, wire->module pointers

---
 passes/hierarchy/submod.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/hierarchy/submod.cc')

diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 84c6b9161..d0c9f4b5a 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -105,7 +105,7 @@ struct SubmodWorker
 
 		RTLIL::Module *new_mod = new RTLIL::Module;
 		new_mod->name = submod.full_name;
-		design->modules_[new_mod->name] = new_mod;
+		design->add(new_mod);
 		int port_counter = 1, auto_name_counter = 1;
 
 		std::set<std::string> all_wire_names;
-- 
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