From 71649969213863b2695f1c51956886fc7879c3e6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 11:12:38 -0700
Subject: RTLIL::S{0,1} -> State::S{0,1}

---
 passes/opt/muxpack.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/opt/muxpack.cc')

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index 6697d6ca1..225c30d9a 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -49,7 +49,7 @@ struct ExclusiveDatabase
 			}
 			else if (cell->type == "$logic_not") {
 				nonconst_sig = sigmap(cell->getPort("\\A"));
-				const_sig = Const(RTLIL::S0, GetSize(nonconst_sig));
+				const_sig = Const(State::S0, GetSize(nonconst_sig));
 				y_port = sigmap(cell->getPort("\\Y"));
 			}
 			else if (cell->type == "$reduce_or") {
-- 
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