From 3f677fb0db15f75d9655fe653f991c94e78a4a1f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Jul 2019 15:54:07 -0700
Subject: Signed extension

---
 passes/pmgen/xilinx_dsp.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'passes/pmgen/xilinx_dsp.cc')

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index a09f96a7f..a4602dd63 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -50,7 +50,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
 
 		if (st.ffA) {
 			SigSpec D = st.ffA->getPort("\\D");
-			cell->setPort("\\A", D.extend_u0(30));
+			cell->setPort("\\A", D.extend_u0(30, true));
 			cell->setParam("\\AREG", State::S1);
 			if (st.ffA->type == "$dff")
 				cell->setPort("\\CEA2", State::S1);
@@ -60,7 +60,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
 		}
 		if (st.ffB) {
 			SigSpec D = st.ffB->getPort("\\D");
-			cell->setPort("\\B", D.extend_u0(18));
+			cell->setPort("\\B", D.extend_u0(18, true));
 			cell->setParam("\\BREG", State::S1);
 			if (st.ffB->type == "$dff")
 				cell->setPort("\\CEB2", State::S1);
-- 
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