From 3f677fb0db15f75d9655fe653f991c94e78a4a1f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Jul 2019 15:54:07 -0700 Subject: Signed extension --- passes/pmgen/xilinx_dsp.pmg | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'passes/pmgen/xilinx_dsp.pmg') diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index ceed64b30..4b7bea308 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -9,10 +9,10 @@ endmatch match ffA select ffA->type.in($dff, $dffe) + select param(ffA, \CLK_POLARITY).as_bool() // select nusers(port(ffA, \Q)) == 2 - index port(ffA, \Q).extend_u0(30) === port(dsp, \A) + index port(ffA, \Q).extend_u0(25, true) === port(dsp, \A).extract(0, 25) // DSP48E1 does not support clock inversion - index param(ffA, \CLK_POLARITY).as_bool() === true optional endmatch @@ -23,9 +23,9 @@ endcode match ffB select ffB->type.in($dff, $dffe) + select param(ffB, \CLK_POLARITY).as_bool() // select nusers(port(ffB, \Q)) == 2 - index port(ffB, \Q).extend_u0(18) === port(dsp, \B) - index param(ffB, \CLK_POLARITY).as_bool() === true + index port(ffB, \Q).extend_u0(18, true) === port(dsp, \B) optional endmatch -- cgit v1.2.3