From 447a31e75d7bd77c0108eb0c76b9749340b10db4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 5 Sep 2019 11:00:27 -0700
Subject: Add support for CEP

---
 passes/pmgen/xilinx_dsp.pmg | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

(limited to 'passes/pmgen/xilinx_dsp.pmg')

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 2681cdbca..a2a6f2ef0 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -2,7 +2,7 @@ pattern xilinx_dsp
 
 state <SigBit> clock
 state <SigSpec> sigA sigffAmux sigB sigffBmux sigC sigM sigP
-state <IdString> ffAmuxAB ffBmuxAB ffMmuxAB postAddAB postAddMuxAB
+state <IdString> ffAmuxAB ffBmuxAB ffMmuxAB ffPmuxAB postAddAB postAddMuxAB
 
 match dsp
 	select dsp->type.in(\DSP48E1)
@@ -120,7 +120,7 @@ match ffMmux
 	filter port(ffMmux, AB) == sigM.extract(0, GetSize(port(ffMmux, \Y)))
 	filter nusers(sigM.extract_end(GetSize(port(ffMmux, AB)))) <= 1
 	set ffMmuxAB AB
-	optional
+	semioptional
 endmatch
 
 code sigM
@@ -199,6 +199,22 @@ code sigC sigP
 	}
 endcode
 
+match ffPmux
+	select ffPmux->type.in($mux)
+	select nusers(port(ffPmux, \Y)) == 2
+	filter GetSize(port(ffPmux, \Y)) <= GetSize(sigP)
+	choice <IdString> AB {\A, \B}
+	filter port(ffPmux, AB) == sigP.extract(0, GetSize(port(ffPmux, \Y)))
+	filter nusers(sigP.extract_end(GetSize(port(ffPmux, AB)))) <= 1
+	set ffPmuxAB AB
+	semioptional
+endmatch
+
+code sigP
+	if (ffPmux)
+		sigP = port(ffPmux, \Y);
+endcode
+
 match ffP
 	if param(dsp, \PREG).as_int() == 0
 	select ffP->type.in($dff)
@@ -207,6 +223,8 @@ match ffP
 	filter GetSize(port(ffP, \D)) >= GetSize(sigP)
 	slice offset GetSize(port(ffP, \D))
 	filter offset+GetSize(sigP) <= GetSize(port(ffP, \D)) && port(ffP, \D).extract(offset, GetSize(sigP)) == sigP
+	// Check ffPmux (when present) is a $dff enable mux
+	filter !ffPmux || port(ffP, \Q) == port(ffPmux, ffPmuxAB == \A ? \B : \A)
 	optional
 endmatch
 
-- 
cgit v1.2.3