From a233762a815fc180b371f699e865a7d7aed77bca Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 22 Jul 2014 19:56:17 +0200
Subject: SigSpec refactoring: renamed chunks and width to __chunks and __width

---
 passes/sat/freduce.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/sat/freduce.cc')

diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index ac0415644..8cc59b291 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -714,7 +714,7 @@ struct FreduceWorker
 
 				if (grp[i].inverted)
 				{
-					if (inv_sig.width == 0)
+					if (inv_sig.__width == 0)
 					{
 						inv_sig = module->addWire(NEW_ID);
 
-- 
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