From 0b308c68357cc85876c3c86d6e5ac8b9318329ca Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 5 Feb 2020 14:46:48 -0800 Subject: abc9_ops: -reintegrate to use derived_type for box_ports --- passes/techmap/abc9_ops.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/techmap/abc9_ops.cc') diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 2b4a5c802..7071f0de4 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -797,7 +797,7 @@ void reintegrate(RTLIL::Module *module) } int input_count = 0, output_count = 0; - for (const auto &port_name : box_ports.at(cell->type)) { + for (const auto &port_name : box_ports.at(derived_type)) { RTLIL::Wire *w = box_module->wire(port_name); log_assert(w); -- cgit v1.2.3