From b7dda723022ad00c6c0089be888eab319953faa8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 14:32:50 +0200 Subject: Changed users of cell->connections_ to the new API (sed command) git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' --- passes/techmap/extract.cc | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'passes/techmap/extract.cc') diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 5dfcd63d1..0d8f6ab0d 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -125,10 +125,10 @@ namespace RTLIL::Wire *lastHaystackWire = NULL; std::map emptyAttr; - for (auto &conn : needleCell->connections_) + for (auto &conn : needleCell->connections()) { RTLIL::SigSpec needleSig = conn.second; - RTLIL::SigSpec haystackSig = haystackCell->connections_.at(portMapping.at(conn.first)); + RTLIL::SigSpec haystackSig = haystackCell->connections().at(portMapping.at(conn.first)); for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) { RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire; @@ -186,7 +186,7 @@ namespace { RTLIL::Cell *cell = cell_it.second; if (!sel || sel->selected(mod, cell)) - for (auto &conn : cell->connections_) { + for (auto &conn : cell->connections()) { RTLIL::SigSpec conn_sig = conn.second; sigmap.apply(conn_sig); for (auto &bit : conn_sig) @@ -207,7 +207,7 @@ namespace type = type.substr(1); graph.createNode(cell->name, type, (void*)cell); - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) { graph.createPort(cell->name, conn.first, conn.second.size()); @@ -257,7 +257,7 @@ namespace { RTLIL::Cell *cell = cell_it.second; if (sel && !sel->selected(mod, cell)) - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) { RTLIL::SigSpec conn_sig = conn.second; sigmap.apply(conn_sig); @@ -305,7 +305,7 @@ namespace if (wire->port_id > 0) { for (int i = 0; i < wire->width; i++) sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair(wire->name, i)); - cell->connections_[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width); + cell->connections()[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width); } } @@ -319,13 +319,13 @@ namespace if (needle_cell == NULL) continue; - for (auto &conn : needle_cell->connections_) { + for (auto &conn : needle_cell->connections()) { RTLIL::SigSpec sig = sigmap(conn.second); if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) { for (int i = 0; i < sig.size(); i++) for (auto &port : sig2port.find(sig[i])) { - RTLIL::SigSpec bitsig = haystack_cell->connections_.at(mapping.portMapping[conn.first]).extract(i, 1); - cell->connections_.at(port.first).replace(port.second, bitsig); + RTLIL::SigSpec bitsig = haystack_cell->connections().at(mapping.portMapping[conn.first]).extract(i, 1); + cell->connections().at(port.first).replace(port.second, bitsig); } } } @@ -714,7 +714,7 @@ struct ExtractPass : public Pass { cells.insert((RTLIL::Cell*)node.userData); for (auto cell : cells) - for (auto &conn : cell->connections_) { + for (auto &conn : cell->connections()) { RTLIL::SigSpec sig = sigmap(conn.second); for (auto &chunk : sig.chunks()) if (chunk.wire != NULL) @@ -739,12 +739,12 @@ struct ExtractPass : public Pass { for (auto cell : cells) { RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type); newCell->parameters = cell->parameters; - for (auto &conn : cell->connections_) { + for (auto &conn : cell->connections()) { std::vector chunks = sigmap(conn.second); for (auto &chunk : chunks) if (chunk.wire != NULL) chunk.wire = newMod->wires.at(chunk.wire->name); - newCell->connections_[conn.first] = chunks; + newCell->connections()[conn.first] = chunks; } } } -- cgit v1.2.3 From f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 15:57:57 +0200 Subject: Manual fixes for new cell connections API --- passes/techmap/extract.cc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'passes/techmap/extract.cc') diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 0d8f6ab0d..6439302cd 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -305,7 +305,7 @@ namespace if (wire->port_id > 0) { for (int i = 0; i < wire->width; i++) sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair(wire->name, i)); - cell->connections()[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width); + cell->set(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width)); } } @@ -325,7 +325,9 @@ namespace for (int i = 0; i < sig.size(); i++) for (auto &port : sig2port.find(sig[i])) { RTLIL::SigSpec bitsig = haystack_cell->connections().at(mapping.portMapping[conn.first]).extract(i, 1); - cell->connections().at(port.first).replace(port.second, bitsig); + RTLIL::SigSpec new_sig = cell->get(port.first); + new_sig.replace(port.second, bitsig); + cell->set(port.first, new_sig); } } } @@ -744,7 +746,7 @@ struct ExtractPass : public Pass { for (auto &chunk : chunks) if (chunk.wire != NULL) chunk.wire = newMod->wires.at(chunk.wire->name); - newCell->connections()[conn.first] = chunks; + newCell->set(conn.first, chunks); } } } -- cgit v1.2.3