From 52355f5185fe42e28775e897f458b38a439c0ec5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 15 Aug 2019 14:50:10 -0700 Subject: Use more ID::{A,B,Y,blackbox,whitebox} --- passes/techmap/extract_reduce.cc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'passes/techmap/extract_reduce.cc') diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index 2ce111b4f..11cfddcd9 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -148,7 +148,7 @@ struct ExtractReducePass : public Pass head_cell = x; - auto y = sigmap(x->getPort(ID(Y))); + auto y = sigmap(x->getPort(ID::Y)); log_assert(y.size() == 1); // Should only continue if there is one fanout back into a cell (not to a port) @@ -166,7 +166,7 @@ struct ExtractReducePass : public Pass { //BFS, following all chains until they hit a cell of a different type //Pick the longest one - auto y = sigmap(cell->getPort(ID(Y))); + auto y = sigmap(cell->getPort(ID::Y)); pool current_loads = sig_to_sink[y]; pool next_loads; @@ -233,7 +233,7 @@ struct ExtractReducePass : public Pass cur_supercell.insert(x); - auto a = sigmap(x->getPort(ID(A))); + auto a = sigmap(x->getPort(ID::A)); log_assert(a.size() == 1); // Must have only one sink unless we're going off chain @@ -249,7 +249,7 @@ struct ExtractReducePass : public Pass } } - auto b = sigmap(x->getPort(ID(B))); + auto b = sigmap(x->getPort(ID::B)); log_assert(b.size() == 1); // Must have only one sink @@ -279,16 +279,16 @@ struct ExtractReducePass : public Pass pool input_pool_intermed; for (auto x : cur_supercell) { - input_pool.insert(sigmap(x->getPort(ID(A)))[0]); - input_pool.insert(sigmap(x->getPort(ID(B)))[0]); - input_pool_intermed.insert(sigmap(x->getPort(ID(Y)))[0]); + input_pool.insert(sigmap(x->getPort(ID::A))[0]); + input_pool.insert(sigmap(x->getPort(ID::B))[0]); + input_pool_intermed.insert(sigmap(x->getPort(ID::Y))[0]); } SigSpec input; for (auto b : input_pool) if (input_pool_intermed.count(b) == 0) input.append_bit(b); - SigBit output = sigmap(head_cell->getPort(ID(Y))[0]); + SigBit output = sigmap(head_cell->getPort(ID::Y)[0]); auto new_reduce_cell = module->addCell(NEW_ID, gt == GateType::And ? ID($reduce_and) : @@ -297,8 +297,8 @@ struct ExtractReducePass : public Pass new_reduce_cell->setParam(ID(A_SIGNED), 0); new_reduce_cell->setParam(ID(A_WIDTH), input.size()); new_reduce_cell->setParam(ID(Y_WIDTH), 1); - new_reduce_cell->setPort(ID(A), input); - new_reduce_cell->setPort(ID(Y), output); + new_reduce_cell->setPort(ID::A, input); + new_reduce_cell->setPort(ID::Y, output); if(allow_off_chain) consumed_cells.insert(head_cell); -- cgit v1.2.3