From 36d94caec169d232e8bf1a668ef9062ab38395ea Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 11:22:09 -0700 Subject: Remove `shregmap -tech xilinx` additions --- passes/techmap/shregmap.cc | 197 ++------------------------------------------- 1 file changed, 8 insertions(+), 189 deletions(-) (limited to 'passes/techmap/shregmap.cc') diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 5e298d8dd..d472d1275 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -26,9 +26,7 @@ PRIVATE_NAMESPACE_BEGIN struct ShregmapTech { virtual ~ShregmapTech() { } - virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {} - virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {} - virtual bool analyze(vector &taps, const vector &qbits) = 0; + virtual bool analyze(vector &taps) = 0; virtual bool fixup(Cell *cell, dict &taps) = 0; }; @@ -56,7 +54,7 @@ struct ShregmapOptions struct ShregmapTechGreenpak4 : ShregmapTech { - bool analyze(vector &taps, const vector &/*qbits*/) + bool analyze(vector &taps) { if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) { taps.clear(); @@ -93,155 +91,6 @@ struct ShregmapTechGreenpak4 : ShregmapTech } }; -struct ShregmapTechXilinx7 : ShregmapTech -{ - dict> sigbit_to_shiftx_offset; - const ShregmapOptions &opts; - - ShregmapTechXilinx7(const ShregmapOptions &opts) : opts(opts) {} - - virtual void init(const Module* module, const SigMap &sigmap) override - { - for (const auto &i : module->cells_) { - auto cell = i.second; - if (cell->type == ID($shiftx)) { - if (cell->getParam(ID(Y_WIDTH)) != 1) continue; - int j = 0; - for (auto bit : sigmap(cell->getPort(ID::A))) - sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, j++, 0); - log_assert(j == cell->getParam(ID(A_WIDTH)).as_int()); - } - else if (cell->type == ID($mux)) { - int j = 0; - for (auto bit : sigmap(cell->getPort(ID::A))) - sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 0, j++); - j = 0; - for (auto bit : sigmap(cell->getPort(ID::B))) - sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 1, j++); - } - } - } - - virtual void non_chain_user(const SigBit &bit, const Cell *cell, IdString port) override - { - auto it = sigbit_to_shiftx_offset.find(bit); - if (it == sigbit_to_shiftx_offset.end()) - return; - if (cell) { - if (cell->type == ID($shiftx) && port == ID::A) - return; - if (cell->type == ID($mux) && port.in(ID::A, ID::B)) - return; - } - sigbit_to_shiftx_offset.erase(it); - } - - virtual bool analyze(vector &taps, const vector &qbits) override - { - if (GetSize(taps) == 1) - return taps[0] >= opts.minlen-1 && sigbit_to_shiftx_offset.count(qbits[0]); - - if (taps.back() < opts.minlen-1) - return false; - - Cell *shiftx = nullptr; - int group = 0; - for (int i = 0; i < GetSize(taps); ++i) { - auto it = sigbit_to_shiftx_offset.find(qbits[i]); - if (it == sigbit_to_shiftx_offset.end()) - return false; - - // Check taps are sequential - if (i != taps[i]) - return false; - // Check taps are not connected to a shift register, - // or sequential to the same shift register - if (i == 0) { - int offset; - std::tie(shiftx,offset,group) = it->second; - if (offset != i) - return false; - } - else { - Cell *shiftx_ = std::get<0>(it->second); - if (shiftx_ != shiftx) - return false; - int offset = std::get<1>(it->second); - if (offset != i) - return false; - int group_ = std::get<2>(it->second); - if (group_ != group) - return false; - } - } - log_assert(shiftx); - - // Only map if $shiftx exclusively covers the shift register - if (shiftx->type == ID($shiftx)) { - if (GetSize(taps) > shiftx->getParam(ID(A_WIDTH)).as_int()) - return false; - // Due to padding the most significant bits of A may be 1'bx, - // and if so, discount them - if (GetSize(taps) < shiftx->getParam(ID(A_WIDTH)).as_int()) { - const SigSpec A = shiftx->getPort(ID::A); - const int A_width = shiftx->getParam(ID(A_WIDTH)).as_int(); - for (int i = GetSize(taps); i < A_width; ++i) - if (A[i] != RTLIL::Sx) return false; - } - else if (GetSize(taps) != shiftx->getParam(ID(A_WIDTH)).as_int()) - return false; - } - else if (shiftx->type == ID($mux)) { - if (GetSize(taps) != 2) - return false; - } - else log_abort(); - - return true; - } - - virtual bool fixup(Cell *cell, dict &taps) override - { - const auto &tap = *taps.begin(); - auto bit = tap.second; - - auto it = sigbit_to_shiftx_offset.find(bit); - log_assert(it != sigbit_to_shiftx_offset.end()); - - auto newcell = cell->module->addCell(NEW_ID, ID($__XILINX_SHREG_)); - newcell->set_src_attribute(cell->get_src_attribute()); - newcell->setParam(ID(DEPTH), cell->getParam(ID(DEPTH))); - newcell->setParam(ID(INIT), cell->getParam(ID(INIT))); - newcell->setParam(ID(CLKPOL), cell->getParam(ID(CLKPOL))); - newcell->setParam(ID(ENPOL), cell->getParam(ID(ENPOL))); - - newcell->setPort(ID(C), cell->getPort(ID(C))); - newcell->setPort(ID(D), cell->getPort(ID(D))); - if (cell->hasPort(ID(E))) - newcell->setPort(ID(E), cell->getPort(ID(E))); - - Cell* shiftx = std::get<0>(it->second); - RTLIL::SigSpec l_wire, q_wire; - if (shiftx->type == ID($shiftx)) { - l_wire = shiftx->getPort(ID::B); - q_wire = shiftx->getPort(ID::Y); - shiftx->setPort(ID::Y, cell->module->addWire(NEW_ID)); - } - else if (shiftx->type == ID($mux)) { - l_wire = shiftx->getPort(ID(S)); - q_wire = shiftx->getPort(ID::Y); - shiftx->setPort(ID::Y, cell->module->addWire(NEW_ID)); - } - else log_abort(); - - newcell->setPort(ID(Q), q_wire); - newcell->setPort(ID(L), l_wire); - - return false; - } -}; - - struct ShregmapWorker { Module *module; @@ -264,10 +113,8 @@ struct ShregmapWorker for (auto wire : module->wires()) { if (wire->port_output || wire->get_bool_attribute(ID::keep)) { - for (auto bit : sigmap(wire)) { + for (auto bit : sigmap(wire)) sigbit_with_non_chain_users.insert(bit); - if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {}); - } } if (wire->attributes.count(ID(init))) { @@ -293,22 +140,10 @@ struct ShregmapWorker if (opts.init || sigbit_init.count(q_bit) == 0) { - auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell)); - if (!r.second) { - // Insertion not successful means that d_bit is already - // connected to another register, thus mark it as a - // non chain user ... + if (sigbit_chain_next.count(d_bit)) { sigbit_with_non_chain_users.insert(d_bit); - // ... and clone d_bit into another wire, and use that - // wire as a different key in the d_bit-to-cell dictionary - // so that it can be identified as another chain - // (omitting this common flop) - // Link: https://github.com/YosysHQ/yosys/pull/1085 - Wire *wire = module->addWire(NEW_ID); - module->connect(wire, d_bit); - sigmap.add(wire, d_bit); - sigbit_chain_next.insert(std::make_pair(wire, cell)); - } + } else + sigbit_chain_next[d_bit] = cell; sigbit_chain_prev[q_bit] = cell; continue; @@ -317,10 +152,8 @@ struct ShregmapWorker for (auto conn : cell->connections()) if (cell->input(conn.first)) - for (auto bit : sigmap(conn.second)) { + for (auto bit : sigmap(conn.second)) sigbit_with_non_chain_users.insert(bit); - if (opts.tech) opts.tech->non_chain_user(bit, cell, conn.first); - } } } @@ -425,7 +258,7 @@ struct ShregmapWorker if (taps.empty() || taps.back() < depth-1) taps.push_back(depth-1); - if (opts.tech->analyze(taps, qbits)) + if (opts.tech->analyze(taps)) break; taps.pop_back(); @@ -544,9 +377,6 @@ struct ShregmapWorker ShregmapWorker(Module *module, const ShregmapOptions &opts) : module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0) { - if (opts.tech) - opts.tech->init(module, sigmap); - make_sigbit_chain_next_prev(); find_chain_start_cells(); @@ -617,11 +447,6 @@ struct ShregmapPass : public Pass { log("\n"); log(" -tech greenpak4\n"); log(" map to greenpak4 shift registers.\n"); - log(" this option also implies -clkpol pos -zinit\n"); - log("\n"); - log(" -tech xilinx\n"); - log(" map to xilinx dynamic-length shift registers.\n"); - log(" this option also implies -params -init\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -676,12 +501,6 @@ struct ShregmapPass : public Pass { clkpol = "pos"; opts.zinit = true; opts.tech = new ShregmapTechGreenpak4; - } - else if (tech == "xilinx") { - opts.init = true; - opts.params = true; - enpol = "any_or_none"; - opts.tech = new ShregmapTechXilinx7(opts); } else { argidx--; break; -- cgit v1.2.3 From e1fff34dde994f6d175311c61c5a63b5a21b549b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 10 Jun 2019 16:16:40 -0700 Subject: If d_bit already in sigbit_chain_next, create extra wire --- passes/techmap/shregmap.cc | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'passes/techmap/shregmap.cc') diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index d472d1275..6c00d4d53 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -140,10 +140,13 @@ struct ShregmapWorker if (opts.init || sigbit_init.count(q_bit) == 0) { - if (sigbit_chain_next.count(d_bit)) { + auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell)); + if (!r.second) { sigbit_with_non_chain_users.insert(d_bit); - } else - sigbit_chain_next[d_bit] = cell; + Wire *wire = module->addWire(NEW_ID); + module->connect(wire, d_bit); + sigbit_chain_next.insert(std::make_pair(wire, cell)); + } sigbit_chain_prev[q_bit] = cell; continue; -- cgit v1.2.3 From 5ff75b1cdce45fdc8422dbe2ac327217a5d2a2e6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 11 Jun 2019 15:48:20 -0700 Subject: Try way that doesn't involve creating a new wire --- passes/techmap/shregmap.cc | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) (limited to 'passes/techmap/shregmap.cc') diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 6c00d4d53..811b40eac 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -141,12 +141,8 @@ struct ShregmapWorker if (opts.init || sigbit_init.count(q_bit) == 0) { auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell)); - if (!r.second) { + if (!r.second) sigbit_with_non_chain_users.insert(d_bit); - Wire *wire = module->addWire(NEW_ID); - module->connect(wire, d_bit); - sigbit_chain_next.insert(std::make_pair(wire, cell)); - } sigbit_chain_prev[q_bit] = cell; continue; @@ -164,14 +160,14 @@ struct ShregmapWorker { for (auto it : sigbit_chain_next) { + Cell *c1, *c2 = it.second; + if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first)) goto start_cell; - if (sigbit_chain_prev.count(it.first) != 0) + c1 = sigbit_chain_prev.at(it.first, nullptr); + if (c1 != nullptr) { - Cell *c1 = sigbit_chain_prev.at(it.first); - Cell *c2 = it.second; - if (c1->type != c2->type) goto start_cell; @@ -181,6 +177,15 @@ struct ShregmapWorker IdString d_port = opts.ffcells.at(c1->type).first; IdString q_port = opts.ffcells.at(c1->type).second; + // If the previous cell's D has other non chain users, + // then it is possible that this previous cell could + // be a start of the chain + SigBit d_bit = sigmap(c1->getPort(d_port).as_bit()); + if (sigbit_with_non_chain_users.count(d_bit)) { + c2 = c1; + goto start_cell; + } + auto c1_conn = c1->connections(); auto c2_conn = c1->connections(); @@ -197,7 +202,7 @@ struct ShregmapWorker } start_cell: - chain_start_cells.insert(it.second); + chain_start_cells.insert(c2); } } -- cgit v1.2.3 From 8691596d19e2384ccf946f2b391bf5c17db0d60e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 11 Jun 2019 16:05:42 -0700 Subject: Revert "Try way that doesn't involve creating a new wire" This reverts commit 2f427acc9ed23c77e89386f4fbf53ac580bf0f0b. --- passes/techmap/shregmap.cc | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) (limited to 'passes/techmap/shregmap.cc') diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 811b40eac..6c00d4d53 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -141,8 +141,12 @@ struct ShregmapWorker if (opts.init || sigbit_init.count(q_bit) == 0) { auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell)); - if (!r.second) + if (!r.second) { sigbit_with_non_chain_users.insert(d_bit); + Wire *wire = module->addWire(NEW_ID); + module->connect(wire, d_bit); + sigbit_chain_next.insert(std::make_pair(wire, cell)); + } sigbit_chain_prev[q_bit] = cell; continue; @@ -160,14 +164,14 @@ struct ShregmapWorker { for (auto it : sigbit_chain_next) { - Cell *c1, *c2 = it.second; - if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first)) goto start_cell; - c1 = sigbit_chain_prev.at(it.first, nullptr); - if (c1 != nullptr) + if (sigbit_chain_prev.count(it.first) != 0) { + Cell *c1 = sigbit_chain_prev.at(it.first); + Cell *c2 = it.second; + if (c1->type != c2->type) goto start_cell; @@ -177,15 +181,6 @@ struct ShregmapWorker IdString d_port = opts.ffcells.at(c1->type).first; IdString q_port = opts.ffcells.at(c1->type).second; - // If the previous cell's D has other non chain users, - // then it is possible that this previous cell could - // be a start of the chain - SigBit d_bit = sigmap(c1->getPort(d_port).as_bit()); - if (sigbit_with_non_chain_users.count(d_bit)) { - c2 = c1; - goto start_cell; - } - auto c1_conn = c1->connections(); auto c2_conn = c1->connections(); @@ -202,7 +197,7 @@ struct ShregmapWorker } start_cell: - chain_start_cells.insert(c2); + chain_start_cells.insert(it.second); } } -- cgit v1.2.3 From cfafd360d52795c9c76c69d008f765d171e2b0ed Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 20 Jun 2019 16:57:54 -0700 Subject: Add comment as per @cliffordwolf --- passes/techmap/shregmap.cc | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'passes/techmap/shregmap.cc') diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 6c00d4d53..f308292fa 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -142,7 +142,18 @@ struct ShregmapWorker { auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell)); if (!r.second) { + // Insertion not successful means that d_bit is already + // connected to another register, thus mark it as a + // non chain user ... sigbit_with_non_chain_users.insert(d_bit); + // ... and clone d_bit into another wire, and use that + // wire as a different key in the d_bit-to-cell dictionary + // so that it can be identified as another chain + // (omitting this common flop) + // Link: https://github.com/YosysHQ/yosys/pull/1085 + // NB: This relies on us not updating sigmap with this + // alias otherwise it would think they are the same + // wire Wire *wire = module->addWire(NEW_ID); module->connect(wire, d_bit); sigbit_chain_next.insert(std::make_pair(wire, cell)); -- cgit v1.2.3 From 53fed4f7e9cd6512762cf93c74464d8e40efb414 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 20 Jun 2019 17:03:05 -0700 Subject: Actually, there might not be any harm in updating sigmap... --- passes/techmap/shregmap.cc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'passes/techmap/shregmap.cc') diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index f308292fa..9da69e8ba 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -151,11 +151,9 @@ struct ShregmapWorker // so that it can be identified as another chain // (omitting this common flop) // Link: https://github.com/YosysHQ/yosys/pull/1085 - // NB: This relies on us not updating sigmap with this - // alias otherwise it would think they are the same - // wire Wire *wire = module->addWire(NEW_ID); module->connect(wire, d_bit); + sigmap.add(wire, d_bit); sigbit_chain_next.insert(std::make_pair(wire, cell)); } -- cgit v1.2.3