From 489caf32c54ee250338eca72c5f0098106d17788 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Wed, 30 Mar 2016 01:07:20 -0700 Subject: Initial work on greenpak4 counter extraction. Doesn't work but a decent start --- passes/techmap/Makefile.inc | 1 + passes/techmap/counters.cc | 220 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 221 insertions(+) create mode 100644 passes/techmap/counters.cc (limited to 'passes') diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 1a34b9eaf..0701e5e10 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -25,6 +25,7 @@ OBJS += passes/techmap/aigmap.o OBJS += passes/techmap/tribuf.o OBJS += passes/techmap/lut2mux.o OBJS += passes/techmap/nlutmap.o +OBJS += passes/techmap/counters.o OBJS += passes/techmap/dffsr2dff.o endif diff --git a/passes/techmap/counters.cc b/passes/techmap/counters.cc new file mode 100644 index 000000000..9e7b7589e --- /dev/null +++ b/passes/techmap/counters.cc @@ -0,0 +1,220 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" +#include "kernel/modtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +//get the list of cells hooked up to at least one bit of a given net +std::set get_other_cells(const RTLIL::SigSpec& port, ModIndex& index, Cell* src) +{ + std::set rval; + for(auto b : port) + { + pool ports = index.query_ports(b); + for(auto x : ports) + { + if(x.cell == src) + continue; + rval.insert(x.cell); + } + } + return rval; +} + +//return true if there is a full-width bus connection between the two named module/port combos +bool is_full_bus(const RTLIL::SigSpec& sig, ModIndex& index, Cell* a, RTLIL::IdString ap, Cell* b, RTLIL::IdString bp) +{ + for(auto s : sig) + { + pool ports = index.query_ports(s); + bool found_a = false; + bool found_b = false; + for(auto x : ports) + { + if( (x.cell == a) && (x.port == ap) ) + found_a = true; + else if( (x.cell == b) && (x.port == bp) ) + found_b = true; + else + return false; + } + + if( (!found_a) || (!found_b) ) + return false; + } + + return true; +} + +//return true if the signal connects to one port only (nothing on the other end) +bool is_unconnected(const RTLIL::SigSpec& port, ModIndex& index) +{ + for(auto b : port) + { + pool ports = index.query_ports(b); + if(ports.size() > 1) + return false; + } + + return true; +} + +void counters_worker(SigMap &sigmap, Module *module, Cell *cell) +{ + if (cell->type == "$alu") + { + //GreenPak does not support counters larger than 14 bits so immediately skip anything bigger + int a_width = cell->getParam("\\A_WIDTH").as_int(); + if(a_width > 14) + return; + + //Second input must be a single bit + int b_width = cell->getParam("\\B_WIDTH").as_int(); + if(b_width != 1) + return; + + //Both inputs must be unsigned, so don't extract anything with a signed input + bool a_sign = cell->getParam("\\A_SIGNED").as_bool(); + bool b_sign = cell->getParam("\\B_SIGNED").as_bool(); + if(a_sign || b_sign) + return; + + //To be a counter, one input of the ALU must be a constant 1 + //TODO: can A or B be swapped in synthesized RTL or is B always the 1? + const RTLIL::SigSpec b_port = sigmap(cell->getPort("\\B")); + if(!b_port.is_fully_const() || (b_port.as_int() != 1) ) + return; + + //BI and CI must be constant 1 as well + const RTLIL::SigSpec bi_port = sigmap(cell->getPort("\\BI")); + if(!bi_port.is_fully_const() || (bi_port.as_int() != 1) ) + return; + const RTLIL::SigSpec ci_port = sigmap(cell->getPort("\\CI")); + if(!ci_port.is_fully_const() || (ci_port.as_int() != 1) ) + return; + + //Index the module + ModIndex index(module); + + //We found a decrementer. Not sure if it's a counter yet but log for debugging + log(" Found candidate counter %s (width %d)\n", cell->name.c_str(), a_width); + + //CO and X must be unconnected (exactly one connection to each port) + if(!is_unconnected(sigmap(cell->getPort("\\CO")), index)) + return; + if(!is_unconnected(sigmap(cell->getPort("\\X")), index)) + return; + + //Y must have exactly one connection, and it has to be a $mux cell. + //We must have a direct bus connection from our Y to their A. + const RTLIL::SigSpec aluy = sigmap(cell->getPort("\\Y")); + std::set y_loads = get_other_cells(aluy, index, cell); + if(y_loads.size() != 1) + return; + Cell* count_mux = *y_loads.begin(); + if(count_mux->type != "$mux") + return; + if(!is_full_bus(aluy, index, cell, "\\Y", count_mux, "\\A")) + return; + + //B connection of the mux is our overflow value + const RTLIL::SigSpec overflow = sigmap(count_mux->getPort("\\B")); + if(!overflow.is_fully_const()) + return; + int count_value = overflow.as_int(); + + //TODO: S connection of the mux must come from an inverter + + //Y connection of the mux must have exactly one load, the counter's internal register + const RTLIL::SigSpec muxy = sigmap(count_mux->getPort("\\Y")); + std::set muxy_loads = get_other_cells(muxy, index, count_mux); + if(muxy_loads.size() != 1) + return; + Cell* count_reg = *muxy_loads.begin(); + if(count_reg->type != "$dff") //TODO: support dffr/dffs? + return; + if(!is_full_bus(muxy, index, count_mux, "\\Y", count_reg, "\\D")) + return; + + log(" Looks like a counter so far (count value = %d, count_reg = %s)\n", + count_value, count_reg->name.c_str()); + + + /* + log("Converting %s cell %s.%s to $adff.\n", log_id(cell->type), log_id(module), log_id(cell)); + + if (GetSize(setctrl) == 1) { + cell->setPort("\\ARST", setctrl); + cell->setParam("\\ARST_POLARITY", setpol); + } else { + cell->setPort("\\ARST", clrctrl); + cell->setParam("\\ARST_POLARITY", clrpol); + } + + cell->type = "$adff"; + cell->unsetPort("\\SET"); + cell->unsetPort("\\CLR"); + cell->setParam("\\ARST_VALUE", reset_val); + cell->unsetParam("\\SET_POLARITY"); + cell->unsetParam("\\CLR_POLARITY"); + + return; + */ + } +} + +struct CountersPass : public Pass { + CountersPass() : Pass("counters", "Extract counter cells") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" counters [options] [selection]\n"); + log("\n"); + log("This pass converts resettable down counters to GreenPak counter cells\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + log_header("Executing COUNTERS pass (mapping counters to GP_COUNTx cells).\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + // if (args[argidx] == "-v") { + // continue; + // } + break; + } + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) { + SigMap sigmap(module); + for (auto cell : module->selected_cells()) + counters_worker(sigmap, module, cell); + } + + } +} CountersPass; + +PRIVATE_NAMESPACE_END -- cgit v1.2.3 From dd7204c0bdb65956fdf27925da3ccfe6f592d012 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Wed, 30 Mar 2016 20:30:03 -0700 Subject: Fixed typo in log message --- passes/opt/opt_muxtree.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 905a01627..f9da807d2 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -68,7 +68,7 @@ struct OptMuxtreeWorker OptMuxtreeWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module), assign_map(module), removed_count(0) { - log("Running muxtree optimizier on module %s..\n", module->name.c_str()); + log("Running muxtree optimizer on module %s..\n", module->name.c_str()); log(" Creating internal representation of mux trees.\n"); -- cgit v1.2.3 From ad19e0c64ab69ab059efc258ae616f4fb5b8847d Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Wed, 30 Mar 2016 21:54:23 -0700 Subject: Continued work on counter extraction. Can recognize compatible RTL counters but not replace with hard macros. --- passes/techmap/counters.cc | 256 +++++++++++++++++++++++++++------------------ 1 file changed, 155 insertions(+), 101 deletions(-) (limited to 'passes') diff --git a/passes/techmap/counters.cc b/passes/techmap/counters.cc index 9e7b7589e..e6e1111c1 100644 --- a/passes/techmap/counters.cc +++ b/passes/techmap/counters.cc @@ -25,9 +25,9 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN //get the list of cells hooked up to at least one bit of a given net -std::set get_other_cells(const RTLIL::SigSpec& port, ModIndex& index, Cell* src) +pool get_other_cells(const RTLIL::SigSpec& port, ModIndex& index, Cell* src) { - std::set rval; + pool rval; for(auto b : port) { pool ports = index.query_ports(b); @@ -41,8 +41,16 @@ std::set get_other_cells(const RTLIL::SigSpec& port, ModIndex& index, Cel return rval; } -//return true if there is a full-width bus connection between the two named module/port combos -bool is_full_bus(const RTLIL::SigSpec& sig, ModIndex& index, Cell* a, RTLIL::IdString ap, Cell* b, RTLIL::IdString bp) +//return true if there is a full-width bus connection from cell a port ap to cell b port bp +//if other_conns_allowed is false, then we require a strict point to point connection (no other links) +bool is_full_bus( + const RTLIL::SigSpec& sig, + ModIndex& index, + Cell* a, + RTLIL::IdString ap, + Cell* b, + RTLIL::IdString bp, + bool other_conns_allowed = false) { for(auto s : sig) { @@ -55,7 +63,7 @@ bool is_full_bus(const RTLIL::SigSpec& sig, ModIndex& index, Cell* a, RTLIL::IdS found_a = true; else if( (x.cell == b) && (x.port == bp) ) found_b = true; - else + else if(!other_conns_allowed) return false; } @@ -79,108 +87,149 @@ bool is_unconnected(const RTLIL::SigSpec& port, ModIndex& index) return true; } -void counters_worker(SigMap &sigmap, Module *module, Cell *cell) +void counters_worker(ModIndex& index, Module */*module*/, Cell *cell, unsigned int& total_counters) { - if (cell->type == "$alu") - { - //GreenPak does not support counters larger than 14 bits so immediately skip anything bigger - int a_width = cell->getParam("\\A_WIDTH").as_int(); - if(a_width > 14) - return; - - //Second input must be a single bit - int b_width = cell->getParam("\\B_WIDTH").as_int(); - if(b_width != 1) - return; - - //Both inputs must be unsigned, so don't extract anything with a signed input - bool a_sign = cell->getParam("\\A_SIGNED").as_bool(); - bool b_sign = cell->getParam("\\B_SIGNED").as_bool(); - if(a_sign || b_sign) - return; - - //To be a counter, one input of the ALU must be a constant 1 - //TODO: can A or B be swapped in synthesized RTL or is B always the 1? - const RTLIL::SigSpec b_port = sigmap(cell->getPort("\\B")); - if(!b_port.is_fully_const() || (b_port.as_int() != 1) ) - return; - - //BI and CI must be constant 1 as well - const RTLIL::SigSpec bi_port = sigmap(cell->getPort("\\BI")); - if(!bi_port.is_fully_const() || (bi_port.as_int() != 1) ) - return; - const RTLIL::SigSpec ci_port = sigmap(cell->getPort("\\CI")); - if(!ci_port.is_fully_const() || (ci_port.as_int() != 1) ) - return; - - //Index the module - ModIndex index(module); - - //We found a decrementer. Not sure if it's a counter yet but log for debugging - log(" Found candidate counter %s (width %d)\n", cell->name.c_str(), a_width); - - //CO and X must be unconnected (exactly one connection to each port) - if(!is_unconnected(sigmap(cell->getPort("\\CO")), index)) - return; - if(!is_unconnected(sigmap(cell->getPort("\\X")), index)) - return; - - //Y must have exactly one connection, and it has to be a $mux cell. - //We must have a direct bus connection from our Y to their A. - const RTLIL::SigSpec aluy = sigmap(cell->getPort("\\Y")); - std::set y_loads = get_other_cells(aluy, index, cell); - if(y_loads.size() != 1) - return; - Cell* count_mux = *y_loads.begin(); - if(count_mux->type != "$mux") - return; - if(!is_full_bus(aluy, index, cell, "\\Y", count_mux, "\\A")) - return; - - //B connection of the mux is our overflow value - const RTLIL::SigSpec overflow = sigmap(count_mux->getPort("\\B")); - if(!overflow.is_fully_const()) - return; - int count_value = overflow.as_int(); + SigMap& sigmap = index.sigmap; + + //Core of the counter must be an ALU + if (cell->type != "$alu") + return; + + //GreenPak does not support counters larger than 14 bits so immediately skip anything bigger + int a_width = cell->getParam("\\A_WIDTH").as_int(); + if(a_width > 14) + return; - //TODO: S connection of the mux must come from an inverter + //Second input must be a single bit + int b_width = cell->getParam("\\B_WIDTH").as_int(); + if(b_width != 1) + return; - //Y connection of the mux must have exactly one load, the counter's internal register - const RTLIL::SigSpec muxy = sigmap(count_mux->getPort("\\Y")); - std::set muxy_loads = get_other_cells(muxy, index, count_mux); - if(muxy_loads.size() != 1) - return; - Cell* count_reg = *muxy_loads.begin(); - if(count_reg->type != "$dff") //TODO: support dffr/dffs? - return; - if(!is_full_bus(muxy, index, count_mux, "\\Y", count_reg, "\\D")) - return; + //Both inputs must be unsigned, so don't extract anything with a signed input + bool a_sign = cell->getParam("\\A_SIGNED").as_bool(); + bool b_sign = cell->getParam("\\B_SIGNED").as_bool(); + if(a_sign || b_sign) + return; + + //To be a counter, one input of the ALU must be a constant 1 + //TODO: can A or B be swapped in synthesized RTL or is B always the 1? + const RTLIL::SigSpec b_port = sigmap(cell->getPort("\\B")); + if(!b_port.is_fully_const() || (b_port.as_int() != 1) ) + return; - log(" Looks like a counter so far (count value = %d, count_reg = %s)\n", - count_value, count_reg->name.c_str()); + //BI and CI must be constant 1 as well + const RTLIL::SigSpec bi_port = sigmap(cell->getPort("\\BI")); + if(!bi_port.is_fully_const() || (bi_port.as_int() != 1) ) + return; + const RTLIL::SigSpec ci_port = sigmap(cell->getPort("\\CI")); + if(!ci_port.is_fully_const() || (ci_port.as_int() != 1) ) + return; + + //CO and X must be unconnected (exactly one connection to each port) + if(!is_unconnected(sigmap(cell->getPort("\\CO")), index)) + return; + if(!is_unconnected(sigmap(cell->getPort("\\X")), index)) + return; + //Y must have exactly one connection, and it has to be a $mux cell. + //We must have a direct bus connection from our Y to their A. + const RTLIL::SigSpec aluy = sigmap(cell->getPort("\\Y")); + pool y_loads = get_other_cells(aluy, index, cell); + if(y_loads.size() != 1) + return; + Cell* count_mux = *y_loads.begin(); + if(count_mux->type != "$mux") + return; + if(!is_full_bus(aluy, index, cell, "\\Y", count_mux, "\\A")) + return; + + //B connection of the mux is our overflow value + const RTLIL::SigSpec overflow = sigmap(count_mux->getPort("\\B")); + if(!overflow.is_fully_const()) + return; + int count_value = overflow.as_int(); + + //S connection of the mux must come from an inverter (need not be the only load) + const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort("\\S")); + pool muxsel_conns = get_other_cells(muxsel, index, count_mux); + Cell* underflow_inv = NULL; + for(auto c : muxsel_conns) + { + if(c->type != "$logic_not") + continue; + if(!is_full_bus(muxsel, index, c, "\\Y", count_mux, "\\S", true)) + continue; + + underflow_inv = c; + break; + } + if(underflow_inv == NULL) + return; + + //Y connection of the mux must have exactly one load, the counter's internal register + const RTLIL::SigSpec muxy = sigmap(count_mux->getPort("\\Y")); + pool muxy_loads = get_other_cells(muxy, index, count_mux); + if(muxy_loads.size() != 1) + return; + Cell* count_reg = *muxy_loads.begin(); + if(count_reg->type != "$dff") //TODO: support dffr/dffs? + return; + if(!is_full_bus(muxy, index, count_mux, "\\Y", count_reg, "\\D")) + return; - /* - log("Converting %s cell %s.%s to $adff.\n", log_id(cell->type), log_id(module), log_id(cell)); + //Register output must have exactly two loads, the inverter and ALU + const RTLIL::SigSpec cnout = sigmap(count_reg->getPort("\\Q")); + pool cnout_loads = get_other_cells(cnout, index, count_reg); + if(cnout_loads.size() != 2) + return; + if(!is_full_bus(cnout, index, count_reg, "\\Q", underflow_inv, "\\A", true)) + return; + if(!is_full_bus(cnout, index, count_reg, "\\Q", cell, "\\A", true)) + return; + + //Register output net must have an INIT attribute equal to the count value + auto rwire = cnout.as_wire(); + if(rwire->attributes.find("\\init") == rwire->attributes.end()) + return; + int rinit = rwire->attributes["\\init"].as_int(); + if(rinit != count_value) + return; + + //Figure out the final cell type based on the counter size + string celltype = "\\GP_COUNT8"; + if(a_width > 8) + celltype = "\\GP_COUNT14"; + + //Log it + total_counters ++; + log(" Extracting %d-bit counter to %s hard macro\n", a_width, celltype.c_str()); + log(" Decrementer: %s\n", cell->name.c_str()); + log(" Output mux: %s\n", count_mux->name.c_str()); + log(" Register: %s\n", count_reg->name.c_str()); + log(" Comparator: %s\n", underflow_inv->name.c_str()); + log(" Count value: %d\n", count_value); + + + /* + log("Converting %s cell %s.%s to $adff.\n", log_id(cell->type), log_id(module), log_id(cell)); - if (GetSize(setctrl) == 1) { - cell->setPort("\\ARST", setctrl); - cell->setParam("\\ARST_POLARITY", setpol); - } else { - cell->setPort("\\ARST", clrctrl); - cell->setParam("\\ARST_POLARITY", clrpol); - } + if (GetSize(setctrl) == 1) { + cell->setPort("\\ARST", setctrl); + cell->setParam("\\ARST_POLARITY", setpol); + } else { + cell->setPort("\\ARST", clrctrl); + cell->setParam("\\ARST_POLARITY", clrpol); + } - cell->type = "$adff"; - cell->unsetPort("\\SET"); - cell->unsetPort("\\CLR"); - cell->setParam("\\ARST_VALUE", reset_val); - cell->unsetParam("\\SET_POLARITY"); - cell->unsetParam("\\CLR_POLARITY"); + cell->type = "$adff"; + cell->unsetPort("\\SET"); + cell->unsetPort("\\CLR"); + cell->setParam("\\ARST_VALUE", reset_val); + cell->unsetParam("\\SET_POLARITY"); + cell->unsetParam("\\CLR_POLARITY"); - return; - */ - } + return; + */ } struct CountersPass : public Pass { @@ -208,12 +257,17 @@ struct CountersPass : public Pass { } extra_args(args, argidx, design); - for (auto module : design->selected_modules()) { - SigMap sigmap(module); + unsigned int total_counters = 0; + for (auto module : design->selected_modules()) + { + ModIndex index(module); for (auto cell : module->selected_cells()) - counters_worker(sigmap, module, cell); + counters_worker(index, module, cell, total_counters); } + if(total_counters) + log("Extracted %u counters\n", total_counters); + } } CountersPass; -- cgit v1.2.3 From 1b42e0c471ba81843e3fbd1869e84b36f8a24c2f Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Wed, 30 Mar 2016 22:03:50 -0700 Subject: Reduced log verbosity --- passes/techmap/counters.cc | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'passes') diff --git a/passes/techmap/counters.cc b/passes/techmap/counters.cc index e6e1111c1..37ddf8430 100644 --- a/passes/techmap/counters.cc +++ b/passes/techmap/counters.cc @@ -202,13 +202,12 @@ void counters_worker(ModIndex& index, Module */*module*/, Cell *cell, unsigned i //Log it total_counters ++; - log(" Extracting %d-bit counter to %s hard macro\n", a_width, celltype.c_str()); - log(" Decrementer: %s\n", cell->name.c_str()); - log(" Output mux: %s\n", count_mux->name.c_str()); - log(" Register: %s\n", count_reg->name.c_str()); - log(" Comparator: %s\n", underflow_inv->name.c_str()); - log(" Count value: %d\n", count_value); - + string count_reg_src = rwire->attributes["\\src"].decode_string().c_str(); + log(" Found %d-bit non-resettable down counter (from %d) for register %s declared at %s\n", + a_width, + count_value, + log_id(rwire->name), + count_reg_src.c_str()); /* log("Converting %s cell %s.%s to $adff.\n", log_id(cell->type), log_id(module), log_id(cell)); @@ -240,12 +239,12 @@ struct CountersPass : public Pass { log("\n"); log(" counters [options] [selection]\n"); log("\n"); - log("This pass converts resettable down counters to GreenPak counter cells\n"); + log("This pass converts resettable down counters to GreenPak4 counter cells\n"); log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { - log_header("Executing COUNTERS pass (mapping counters to GP_COUNTx cells).\n"); + log_header("Executing COUNTERS pass (mapping counters to hard IP blocks).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) -- cgit v1.2.3 From 1ae33344f4f18f4fbb899e4635659bf1cd8f0448 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Wed, 30 Mar 2016 22:40:14 -0700 Subject: Added initial implementation of "counters" pass to synth_greenpak4. Can only infer non-resettable down counters for now. --- passes/techmap/counters.cc | 62 +++++++++++++++++++++++++++------------------- 1 file changed, 37 insertions(+), 25 deletions(-) (limited to 'passes') diff --git a/passes/techmap/counters.cc b/passes/techmap/counters.cc index 37ddf8430..65cef6a75 100644 --- a/passes/techmap/counters.cc +++ b/passes/techmap/counters.cc @@ -87,7 +87,7 @@ bool is_unconnected(const RTLIL::SigSpec& port, ModIndex& index) return true; } -void counters_worker(ModIndex& index, Module */*module*/, Cell *cell, unsigned int& total_counters) +void counters_worker(ModIndex& index, Module *module, Cell *cell, unsigned int& total_counters) { SigMap& sigmap = index.sigmap; @@ -143,11 +143,11 @@ void counters_worker(ModIndex& index, Module */*module*/, Cell *cell, unsigned i if(!is_full_bus(aluy, index, cell, "\\Y", count_mux, "\\A")) return; - //B connection of the mux is our overflow value - const RTLIL::SigSpec overflow = sigmap(count_mux->getPort("\\B")); - if(!overflow.is_fully_const()) + //B connection of the mux is our underflow value + const RTLIL::SigSpec underflow = sigmap(count_mux->getPort("\\B")); + if(!underflow.is_fully_const()) return; - int count_value = overflow.as_int(); + int count_value = underflow.as_int(); //S connection of the mux must come from an inverter (need not be the only load) const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort("\\S")); @@ -186,6 +186,9 @@ void counters_worker(ModIndex& index, Module */*module*/, Cell *cell, unsigned i return; if(!is_full_bus(cnout, index, count_reg, "\\Q", cell, "\\A", true)) return; + + //Look up the clock from the register + const RTLIL::SigSpec clk = sigmap(count_reg->getPort("\\CLK")); //Register output net must have an INIT attribute equal to the count value auto rwire = cnout.as_wire(); @@ -208,27 +211,36 @@ void counters_worker(ModIndex& index, Module */*module*/, Cell *cell, unsigned i count_value, log_id(rwire->name), count_reg_src.c_str()); + + //Wipe all of the old connections to the ALU + cell->unsetPort("\\A"); + cell->unsetPort("\\B"); + cell->unsetPort("\\BI"); + cell->unsetPort("\\CI"); + cell->unsetPort("\\CO"); + cell->unsetPort("\\X"); + cell->unsetPort("\\Y"); + cell->unsetParam("\\A_SIGNED"); + cell->unsetParam("\\A_WIDTH"); + cell->unsetParam("\\B_SIGNED"); + cell->unsetParam("\\B_WIDTH"); + cell->unsetParam("\\Y_WIDTH"); - /* - log("Converting %s cell %s.%s to $adff.\n", log_id(cell->type), log_id(module), log_id(cell)); - - if (GetSize(setctrl) == 1) { - cell->setPort("\\ARST", setctrl); - cell->setParam("\\ARST_POLARITY", setpol); - } else { - cell->setPort("\\ARST", clrctrl); - cell->setParam("\\ARST_POLARITY", clrpol); - } - - cell->type = "$adff"; - cell->unsetPort("\\SET"); - cell->unsetPort("\\CLR"); - cell->setParam("\\ARST_VALUE", reset_val); - cell->unsetParam("\\SET_POLARITY"); - cell->unsetParam("\\CLR_POLARITY"); - - return; - */ + //Change the cell type + cell->type = celltype; + + //Hook it up to everything + cell->setParam("\\RESET_MODE", RTLIL::Const("RISING")); + cell->setParam("\\CLKIN_DIVIDE", RTLIL::Const(1)); + cell->setParam("\\COUNT_TO", RTLIL::Const(count_value)); + cell->setPort("\\CLK", clk); + cell->setPort("\\RST", RTLIL::SigSpec(false)); + cell->setPort("\\OUT", muxsel); + + //Delete the cells we've replaced (let opt_clean handle deleting the now-redundant wires) + module->remove(count_mux); + module->remove(count_reg); + module->remove(underflow_inv); } struct CountersPass : public Pass { -- cgit v1.2.3 From 984561c034bac0b996d8b2201105a795c6c0e00d Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Wed, 30 Mar 2016 22:52:01 -0700 Subject: Renamed counters pass to greenpak4_counters --- passes/techmap/Makefile.inc | 1 - passes/techmap/counters.cc | 285 -------------------------------------------- 2 files changed, 286 deletions(-) delete mode 100644 passes/techmap/counters.cc (limited to 'passes') diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 0701e5e10..1a34b9eaf 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -25,7 +25,6 @@ OBJS += passes/techmap/aigmap.o OBJS += passes/techmap/tribuf.o OBJS += passes/techmap/lut2mux.o OBJS += passes/techmap/nlutmap.o -OBJS += passes/techmap/counters.o OBJS += passes/techmap/dffsr2dff.o endif diff --git a/passes/techmap/counters.cc b/passes/techmap/counters.cc deleted file mode 100644 index 65cef6a75..000000000 --- a/passes/techmap/counters.cc +++ /dev/null @@ -1,285 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/yosys.h" -#include "kernel/sigtools.h" -#include "kernel/modtools.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -//get the list of cells hooked up to at least one bit of a given net -pool get_other_cells(const RTLIL::SigSpec& port, ModIndex& index, Cell* src) -{ - pool rval; - for(auto b : port) - { - pool ports = index.query_ports(b); - for(auto x : ports) - { - if(x.cell == src) - continue; - rval.insert(x.cell); - } - } - return rval; -} - -//return true if there is a full-width bus connection from cell a port ap to cell b port bp -//if other_conns_allowed is false, then we require a strict point to point connection (no other links) -bool is_full_bus( - const RTLIL::SigSpec& sig, - ModIndex& index, - Cell* a, - RTLIL::IdString ap, - Cell* b, - RTLIL::IdString bp, - bool other_conns_allowed = false) -{ - for(auto s : sig) - { - pool ports = index.query_ports(s); - bool found_a = false; - bool found_b = false; - for(auto x : ports) - { - if( (x.cell == a) && (x.port == ap) ) - found_a = true; - else if( (x.cell == b) && (x.port == bp) ) - found_b = true; - else if(!other_conns_allowed) - return false; - } - - if( (!found_a) || (!found_b) ) - return false; - } - - return true; -} - -//return true if the signal connects to one port only (nothing on the other end) -bool is_unconnected(const RTLIL::SigSpec& port, ModIndex& index) -{ - for(auto b : port) - { - pool ports = index.query_ports(b); - if(ports.size() > 1) - return false; - } - - return true; -} - -void counters_worker(ModIndex& index, Module *module, Cell *cell, unsigned int& total_counters) -{ - SigMap& sigmap = index.sigmap; - - //Core of the counter must be an ALU - if (cell->type != "$alu") - return; - - //GreenPak does not support counters larger than 14 bits so immediately skip anything bigger - int a_width = cell->getParam("\\A_WIDTH").as_int(); - if(a_width > 14) - return; - - //Second input must be a single bit - int b_width = cell->getParam("\\B_WIDTH").as_int(); - if(b_width != 1) - return; - - //Both inputs must be unsigned, so don't extract anything with a signed input - bool a_sign = cell->getParam("\\A_SIGNED").as_bool(); - bool b_sign = cell->getParam("\\B_SIGNED").as_bool(); - if(a_sign || b_sign) - return; - - //To be a counter, one input of the ALU must be a constant 1 - //TODO: can A or B be swapped in synthesized RTL or is B always the 1? - const RTLIL::SigSpec b_port = sigmap(cell->getPort("\\B")); - if(!b_port.is_fully_const() || (b_port.as_int() != 1) ) - return; - - //BI and CI must be constant 1 as well - const RTLIL::SigSpec bi_port = sigmap(cell->getPort("\\BI")); - if(!bi_port.is_fully_const() || (bi_port.as_int() != 1) ) - return; - const RTLIL::SigSpec ci_port = sigmap(cell->getPort("\\CI")); - if(!ci_port.is_fully_const() || (ci_port.as_int() != 1) ) - return; - - //CO and X must be unconnected (exactly one connection to each port) - if(!is_unconnected(sigmap(cell->getPort("\\CO")), index)) - return; - if(!is_unconnected(sigmap(cell->getPort("\\X")), index)) - return; - - //Y must have exactly one connection, and it has to be a $mux cell. - //We must have a direct bus connection from our Y to their A. - const RTLIL::SigSpec aluy = sigmap(cell->getPort("\\Y")); - pool y_loads = get_other_cells(aluy, index, cell); - if(y_loads.size() != 1) - return; - Cell* count_mux = *y_loads.begin(); - if(count_mux->type != "$mux") - return; - if(!is_full_bus(aluy, index, cell, "\\Y", count_mux, "\\A")) - return; - - //B connection of the mux is our underflow value - const RTLIL::SigSpec underflow = sigmap(count_mux->getPort("\\B")); - if(!underflow.is_fully_const()) - return; - int count_value = underflow.as_int(); - - //S connection of the mux must come from an inverter (need not be the only load) - const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort("\\S")); - pool muxsel_conns = get_other_cells(muxsel, index, count_mux); - Cell* underflow_inv = NULL; - for(auto c : muxsel_conns) - { - if(c->type != "$logic_not") - continue; - if(!is_full_bus(muxsel, index, c, "\\Y", count_mux, "\\S", true)) - continue; - - underflow_inv = c; - break; - } - if(underflow_inv == NULL) - return; - - //Y connection of the mux must have exactly one load, the counter's internal register - const RTLIL::SigSpec muxy = sigmap(count_mux->getPort("\\Y")); - pool muxy_loads = get_other_cells(muxy, index, count_mux); - if(muxy_loads.size() != 1) - return; - Cell* count_reg = *muxy_loads.begin(); - if(count_reg->type != "$dff") //TODO: support dffr/dffs? - return; - if(!is_full_bus(muxy, index, count_mux, "\\Y", count_reg, "\\D")) - return; - - //Register output must have exactly two loads, the inverter and ALU - const RTLIL::SigSpec cnout = sigmap(count_reg->getPort("\\Q")); - pool cnout_loads = get_other_cells(cnout, index, count_reg); - if(cnout_loads.size() != 2) - return; - if(!is_full_bus(cnout, index, count_reg, "\\Q", underflow_inv, "\\A", true)) - return; - if(!is_full_bus(cnout, index, count_reg, "\\Q", cell, "\\A", true)) - return; - - //Look up the clock from the register - const RTLIL::SigSpec clk = sigmap(count_reg->getPort("\\CLK")); - - //Register output net must have an INIT attribute equal to the count value - auto rwire = cnout.as_wire(); - if(rwire->attributes.find("\\init") == rwire->attributes.end()) - return; - int rinit = rwire->attributes["\\init"].as_int(); - if(rinit != count_value) - return; - - //Figure out the final cell type based on the counter size - string celltype = "\\GP_COUNT8"; - if(a_width > 8) - celltype = "\\GP_COUNT14"; - - //Log it - total_counters ++; - string count_reg_src = rwire->attributes["\\src"].decode_string().c_str(); - log(" Found %d-bit non-resettable down counter (from %d) for register %s declared at %s\n", - a_width, - count_value, - log_id(rwire->name), - count_reg_src.c_str()); - - //Wipe all of the old connections to the ALU - cell->unsetPort("\\A"); - cell->unsetPort("\\B"); - cell->unsetPort("\\BI"); - cell->unsetPort("\\CI"); - cell->unsetPort("\\CO"); - cell->unsetPort("\\X"); - cell->unsetPort("\\Y"); - cell->unsetParam("\\A_SIGNED"); - cell->unsetParam("\\A_WIDTH"); - cell->unsetParam("\\B_SIGNED"); - cell->unsetParam("\\B_WIDTH"); - cell->unsetParam("\\Y_WIDTH"); - - //Change the cell type - cell->type = celltype; - - //Hook it up to everything - cell->setParam("\\RESET_MODE", RTLIL::Const("RISING")); - cell->setParam("\\CLKIN_DIVIDE", RTLIL::Const(1)); - cell->setParam("\\COUNT_TO", RTLIL::Const(count_value)); - cell->setPort("\\CLK", clk); - cell->setPort("\\RST", RTLIL::SigSpec(false)); - cell->setPort("\\OUT", muxsel); - - //Delete the cells we've replaced (let opt_clean handle deleting the now-redundant wires) - module->remove(count_mux); - module->remove(count_reg); - module->remove(underflow_inv); -} - -struct CountersPass : public Pass { - CountersPass() : Pass("counters", "Extract counter cells") { } - virtual void help() - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" counters [options] [selection]\n"); - log("\n"); - log("This pass converts resettable down counters to GreenPak4 counter cells\n"); - log("\n"); - } - virtual void execute(std::vector args, RTLIL::Design *design) - { - log_header("Executing COUNTERS pass (mapping counters to hard IP blocks).\n"); - - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) - { - // if (args[argidx] == "-v") { - // continue; - // } - break; - } - extra_args(args, argidx, design); - - unsigned int total_counters = 0; - for (auto module : design->selected_modules()) - { - ModIndex index(module); - for (auto cell : module->selected_cells()) - counters_worker(index, module, cell, total_counters); - } - - if(total_counters) - log("Extracted %u counters\n", total_counters); - - } -} CountersPass; - -PRIVATE_NAMESPACE_END -- cgit v1.2.3