From c2b7ad3b28ebd7865c8b2e795b2942d5d1bd00f5 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 17 Dec 2021 20:25:32 +0800 Subject: anlogic: support BRAM mapping Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng --- techlibs/anlogic/brams_init.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 techlibs/anlogic/brams_init.py (limited to 'techlibs/anlogic/brams_init.py') diff --git a/techlibs/anlogic/brams_init.py b/techlibs/anlogic/brams_init.py new file mode 100644 index 000000000..8dda0d33e --- /dev/null +++ b/techlibs/anlogic/brams_init.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 + +with open("techlibs/anlogic/brams_init_9.vh", "w") as f: + for i in range(4): + init_snippets = [" INIT[%3d*9+8]" % (k+256*i,) for k in range(255, -1, -1)] + for k in range(4, 256, 4): + init_snippets[k] = "\n " + init_snippets[k] + print(".INITP_%02X({%s})," % (i, ",".join(init_snippets)), file=f) + for i in range(32): + init_snippets = [" INIT[%3d*9 +: 8]" % (k+32*i,) for k in range(31, -1, -1)] + for k in range(4, 32, 4): + init_snippets[k] = "\n " + init_snippets[k] + print(".INIT_%02X({%s})," % (i, ",".join(init_snippets)), file=f) + +with open("techlibs/anlogic/brams_init_8.vh", "w") as f: + for i in range(32): + print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f) + +with open("techlibs/anlogic/brams_init_16.vh", "w") as f: + for i in range(128): + print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f) -- cgit v1.2.3