From 269ff450f55f4354c82db1b98f8eb722317d9250 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 8 Jul 2019 15:40:12 +0100 Subject: Add mul2dsp multiplier splitting rule and ECP5 mapping Signed-off-by: David Shah --- techlibs/common/mul2dsp.v | 237 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 237 insertions(+) create mode 100644 techlibs/common/mul2dsp.v (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v new file mode 100644 index 000000000..37ce2e485 --- /dev/null +++ b/techlibs/common/mul2dsp.v @@ -0,0 +1,237 @@ +// From Eddie Hung +// extracted from: https://github.com/eddiehung/vtr-with-yosys/blob/vtr7-with-yosys/vtr_flow/misc/yosys_models.v#L220 +// revised by Andre DeHon +// further revised by David Shah +`ifndef DSP_A_MAXWIDTH +`define DSP_A_MAXWIDTH 18 +`endif +`ifndef DSP_A_MAXWIDTH +`define DSP_B_MAXWIDTH 25 +`endif + +`ifndef ADDER_MINWIDTH +`define ADDER_MINWIDTH AAA +`endif + +`ifndef DSP_NAME +`define DSP_NAME M18x25 +`endif + +`define MAX(a,b) (a > b ? a : b) +`define MIN(a,b) (a < b ? a : b) + +(* techmap_celltype = "$mul" *) +module \$mul (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y; + + wire [1023:0] _TECHMAP_DO_ = "proc; clean"; + + generate + if (A_WIDTH `DSP_A_MAXWIDTH) begin + localparam n_floored = A_WIDTH/`DSP_A_MAXWIDTH; + localparam n = n_floored + (n_floored*`DSP_A_MAXWIDTH < A_WIDTH ? 1 : 0); + wire [`DSP_A_MAXWIDTH+B_WIDTH-1:0] partial [n-1:1]; + wire [Y_WIDTH-1:0] partial_sum [n-2:0]; + + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(`DSP_A_MAXWIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(B_WIDTH+`DSP_A_MAXWIDTH) + ) mul_slice_first ( + .A(A[`DSP_A_MAXWIDTH-1:0]), + .B(B), + .Y(partial_sum[0][B_WIDTH+`DSP_A_MAXWIDTH-1:0]) + ); + assign partial_sum[0][Y_WIDTH-1:B_WIDTH+`DSP_A_MAXWIDTH]=0; + + genvar i; + generate + for (i = 1; i < n-1; i=i+1) begin:slice + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(`DSP_A_MAXWIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(B_WIDTH+`DSP_A_MAXWIDTH) + ) mul_slice ( + .A(A[(i+1)*`DSP_A_MAXWIDTH-1:i*`DSP_A_MAXWIDTH]), + .B(B), + .Y(partial[i][B_WIDTH+`DSP_A_MAXWIDTH-1:0]) + ); + //assign partial_sum[i] = (partial[i] << i*`DSP_A_MAXWIDTH) + partial_sum[i-1]; + assign partial_sum[i] = { + partial[i][B_WIDTH+`DSP_A_MAXWIDTH-1:0] + + partial_sum[i-1][Y_WIDTH-1:(i*`DSP_A_MAXWIDTH)], + partial_sum[i-1][(i*`DSP_A_MAXWIDTH)-1:0] + }; + end + endgenerate + + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH), + ) mul_slice_last ( + .A(A[A_WIDTH-1:(n-1)*`DSP_A_MAXWIDTH]), + .B(B), + .Y(partial[n-1][A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH-1:0]) + ); + //assign Y = (partial[n-1] << (n-1)*`DSP_A_MAXWIDTH) + partial_sum[n-2]; + assign Y = { + partial[n-1][A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH:0] + + partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_A_MAXWIDTH)], + partial_sum[n-2][((n-1)*`DSP_A_MAXWIDTH)-1:0] + }; + end + else if (B_WIDTH > `DSP_B_MAXWIDTH) begin + localparam n_floored = B_WIDTH/`DSP_B_MAXWIDTH; + localparam n = n_floored + (n_floored*`DSP_B_MAXWIDTH < B_WIDTH ? 1 : 0); + wire [A_WIDTH+`DSP_B_MAXWIDTH-1:0] partial [n-1:1]; + wire [Y_WIDTH-1:0] partial_sum [n-2:0]; + + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(`DSP_B_MAXWIDTH), + .Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH) + ) mul_first ( + .A(A), + .B(B[`DSP_B_MAXWIDTH-1:0]), + .Y(partial_sum[0][A_WIDTH+`DSP_B_MAXWIDTH-1:0]) + ); + assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0; + + genvar i; + generate + for (i = 1; i < n-1; i=i+1) begin:slice + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(`DSP_B_MAXWIDTH), + .Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH) + ) mul ( + .A(A), + .B(B[(i+1)*`DSP_B_MAXWIDTH-1:i*`DSP_B_MAXWIDTH]), + .Y(partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:0]) + ); + //assign partial_sum[i] = (partial[i] << i*`DSP_B_MAXWIDTH) + partial_sum[i-1]; + // was: + //assign partial_sum[i] = { + // partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], + // partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)], + // partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0] + assign partial_sum[i] = { + partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:0] + + partial_sum[i-1][Y_WIDTH-1:(i*`DSP_B_MAXWIDTH)], + partial_sum[i-1][(i*`DSP_B_MAXWIDTH)-1:0] + }; + end + endgenerate + + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH-(n-1)*`DSP_B_MAXWIDTH), + .Y_WIDTH(A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH) + ) mul_last ( + .A(A), + .B(B[B_WIDTH-1:(n-1)*`DSP_B_MAXWIDTH]), + .Y(partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0]) + ); + // AMD: this came comment out -- looks closer to right answer + //assign Y = (partial[n-1] << (n-1)*`DSP_B_MAXWIDTH) + partial_sum[n-2]; + // was (looks broken) + //assign Y = { + // partial[n-1][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], + // partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)], + // partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0] + assign Y = { + partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0] + + partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_B_MAXWIDTH)], + partial_sum[n-2][((n-1)*`DSP_B_MAXWIDTH)-1:0] + }; + end + else begin + wire [A_WIDTH+B_WIDTH-1:0] out; + wire [(`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)-(A_WIDTH+B_WIDTH)-1:0] dummy; + wire Asign, Bsign; + assign Asign = (A_SIGNED ? A[A_WIDTH-1] : 1'b0); + assign Bsign = (B_SIGNED ? B[B_WIDTH-1] : 1'b0); + `DSP_NAME _TECHMAP_REPLACE_ ( + .A({ {{`DSP_A_MAXWIDTH-A_WIDTH}{Asign}}, A }), + .B({ {{`DSP_B_MAXWIDTH-B_WIDTH}{Bsign}}, B }), + .OUT({dummy, out}) + ); + if (Y_WIDTH < A_WIDTH+B_WIDTH) + assign Y = out[Y_WIDTH-1:0]; + else begin + wire Ysign = (A_SIGNED || B_SIGNED ? out[A_WIDTH+BWIDTH-1] : 1'b0); + assign Y = { {{Y_WIDTH-(A_WIDTH+B_WIDTH)}{Ysign}}, out[A_WIDTH+B_WIDTH-1:0] }; + end + end + endgenerate +endmodule + + -- cgit v1.2.3 From e78864993adab41492670c089f6365088426726f Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 8 Jul 2019 15:43:48 +0100 Subject: mul2dsp: Fix typo Signed-off-by: David Shah --- techlibs/common/mul2dsp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 37ce2e485..ece45db79 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -227,7 +227,7 @@ module \$__mul_gen (A, B, Y); if (Y_WIDTH < A_WIDTH+B_WIDTH) assign Y = out[Y_WIDTH-1:0]; else begin - wire Ysign = (A_SIGNED || B_SIGNED ? out[A_WIDTH+BWIDTH-1] : 1'b0); + wire Ysign = (A_SIGNED || B_SIGNED ? out[A_WIDTH+B_WIDTH-1] : 1'b0); assign Y = { {{Y_WIDTH-(A_WIDTH+B_WIDTH)}{Ysign}}, out[A_WIDTH+B_WIDTH-1:0] }; end end -- cgit v1.2.3 From 1793e6018a37af674a356769779674e095fae261 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Jul 2019 11:19:54 -0700 Subject: Tidy up --- techlibs/common/mul2dsp.v | 65 +++++++++++++++++++---------------------------- 1 file changed, 26 insertions(+), 39 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index ece45db79..d2e68987b 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -32,40 +32,32 @@ module \$mul (A, B, Y); input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; - wire [1023:0] _TECHMAP_DO_ = "proc; clean"; - - generate - if (A_WIDTH `DSP_A_MAXWIDTH) begin + if (A_WIDTH > `DSP_A_MAXWIDTH) begin localparam n_floored = A_WIDTH/`DSP_A_MAXWIDTH; localparam n = n_floored + (n_floored*`DSP_A_MAXWIDTH < A_WIDTH ? 1 : 0); wire [`DSP_A_MAXWIDTH+B_WIDTH-1:0] partial [n-1:1]; @@ -101,8 +94,6 @@ module \$__mul_gen (A, B, Y); ); assign partial_sum[0][Y_WIDTH-1:B_WIDTH+`DSP_A_MAXWIDTH]=0; - genvar i; - generate for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( .A_SIGNED(A_SIGNED), @@ -122,7 +113,6 @@ module \$__mul_gen (A, B, Y); partial_sum[i-1][(i*`DSP_A_MAXWIDTH)-1:0] }; end - endgenerate \$__mul_gen #( .A_SIGNED(A_SIGNED), @@ -161,8 +151,6 @@ module \$__mul_gen (A, B, Y); ); assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0; - genvar i; - generate for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( .A_SIGNED(A_SIGNED), @@ -187,7 +175,6 @@ module \$__mul_gen (A, B, Y); partial_sum[i-1][(i*`DSP_B_MAXWIDTH)-1:0] }; end - endgenerate \$__mul_gen #( .A_SIGNED(A_SIGNED), -- cgit v1.2.3 From 91fcf034bceecd50f1aaf96c3cdc270250ab9597 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Jul 2019 11:24:11 -0700 Subject: Only swap if B_WIDTH > A_WIDTH --- techlibs/common/mul2dsp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index d2e68987b..0eec4cc82 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -33,7 +33,7 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (A_WIDTH < B_WIDTH) + if (B_WIDTH < A_WIDTH) \$__mul_gen #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), -- cgit v1.2.3 From 42f8e68e76a3717cf4ad29c36f0a9a801cde52c1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Jul 2019 14:45:47 -0700 Subject: OUT port to Y in generic DSP --- techlibs/common/mul2dsp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 0eec4cc82..0a87716d9 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -209,7 +209,7 @@ module \$__mul_gen (A, B, Y); `DSP_NAME _TECHMAP_REPLACE_ ( .A({ {{`DSP_A_MAXWIDTH-A_WIDTH}{Asign}}, A }), .B({ {{`DSP_B_MAXWIDTH-B_WIDTH}{Bsign}}, B }), - .OUT({dummy, out}) + .Y({dummy, out}) ); if (Y_WIDTH < A_WIDTH+B_WIDTH) assign Y = out[Y_WIDTH-1:0]; -- cgit v1.2.3 From fd5b3593d8496578c0879fc024bf81737be3702f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Jul 2019 16:52:37 -0700 Subject: Do not swap if equals --- techlibs/common/mul2dsp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 0a87716d9..046f84320 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -33,7 +33,7 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (B_WIDTH < A_WIDTH) + if (A_WIDTH >= B_WIDTH) \$__mul_gen #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), -- cgit v1.2.3 From 7a75f5f3ac82aa764f41e8fbb93475ab729750dc Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 16 Jul 2019 16:19:32 +0100 Subject: mul2dsp: Fix indentation Signed-off-by: David Shah --- techlibs/common/mul2dsp.v | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 0eec4cc82..69de74cad 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -92,7 +92,7 @@ module \$__mul_gen (A, B, Y); .B(B), .Y(partial_sum[0][B_WIDTH+`DSP_A_MAXWIDTH-1:0]) ); - assign partial_sum[0][Y_WIDTH-1:B_WIDTH+`DSP_A_MAXWIDTH]=0; + assign partial_sum[0][Y_WIDTH-1:B_WIDTH+`DSP_A_MAXWIDTH]=0; for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( @@ -149,7 +149,7 @@ module \$__mul_gen (A, B, Y); .B(B[`DSP_B_MAXWIDTH-1:0]), .Y(partial_sum[0][A_WIDTH+`DSP_B_MAXWIDTH-1:0]) ); - assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0; + assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0; for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( @@ -157,14 +157,14 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), - .Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH) + .Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH) ) mul ( .A(A), .B(B[(i+1)*`DSP_B_MAXWIDTH-1:i*`DSP_B_MAXWIDTH]), .Y(partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:0]) ); //assign partial_sum[i] = (partial[i] << i*`DSP_B_MAXWIDTH) + partial_sum[i-1]; - // was: + // was: //assign partial_sum[i] = { // partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], // partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)], @@ -187,14 +187,14 @@ module \$__mul_gen (A, B, Y); .B(B[B_WIDTH-1:(n-1)*`DSP_B_MAXWIDTH]), .Y(partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0]) ); - // AMD: this came comment out -- looks closer to right answer + // AMD: this came comment out -- looks closer to right answer //assign Y = (partial[n-1] << (n-1)*`DSP_B_MAXWIDTH) + partial_sum[n-2]; - // was (looks broken) + // was (looks broken) //assign Y = { // partial[n-1][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], // partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)], // partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0] - assign Y = { + assign Y = { partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_B_MAXWIDTH)], partial_sum[n-2][((n-1)*`DSP_B_MAXWIDTH)-1:0] -- cgit v1.2.3 From 8da4c1ad8262216c5204c735f5297da33fed01fa Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 16 Jul 2019 16:44:40 +0100 Subject: mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH Signed-off-by: David Shah --- techlibs/common/mul2dsp.v | 40 ++++++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 18 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 69de74cad..262e29986 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -80,19 +80,21 @@ module \$__mul_gen (A, B, Y); localparam n = n_floored + (n_floored*`DSP_A_MAXWIDTH < A_WIDTH ? 1 : 0); wire [`DSP_A_MAXWIDTH+B_WIDTH-1:0] partial [n-1:1]; wire [Y_WIDTH-1:0] partial_sum [n-2:0]; + localparam int_yw = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); \$__mul_gen #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), - .Y_WIDTH(B_WIDTH+`DSP_A_MAXWIDTH) + .Y_WIDTH(int_yw) ) mul_slice_first ( .A(A[`DSP_A_MAXWIDTH-1:0]), .B(B), - .Y(partial_sum[0][B_WIDTH+`DSP_A_MAXWIDTH-1:0]) + .Y(partial_sum[0][int_yw-1:0]) ); - assign partial_sum[0][Y_WIDTH-1:B_WIDTH+`DSP_A_MAXWIDTH]=0; + if (Y_WIDTH > int_yw) + assign partial_sum[0][Y_WIDTH-1:int_yw]=0; for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( @@ -100,15 +102,15 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), - .Y_WIDTH(B_WIDTH+`DSP_A_MAXWIDTH) + .Y_WIDTH(int_yw) ) mul_slice ( .A(A[(i+1)*`DSP_A_MAXWIDTH-1:i*`DSP_A_MAXWIDTH]), .B(B), - .Y(partial[i][B_WIDTH+`DSP_A_MAXWIDTH-1:0]) + .Y(partial[i][int_yw-1:0]) ); //assign partial_sum[i] = (partial[i] << i*`DSP_A_MAXWIDTH) + partial_sum[i-1]; assign partial_sum[i] = { - partial[i][B_WIDTH+`DSP_A_MAXWIDTH-1:0] + partial[i][int_yw-1:0] + partial_sum[i-1][Y_WIDTH-1:(i*`DSP_A_MAXWIDTH)], partial_sum[i-1][(i*`DSP_A_MAXWIDTH)-1:0] }; @@ -119,15 +121,15 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), - .Y_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH), + .Y_WIDTH(`MIN(Y_WIDTH, A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH)), ) mul_slice_last ( .A(A[A_WIDTH-1:(n-1)*`DSP_A_MAXWIDTH]), .B(B), - .Y(partial[n-1][A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH-1:0]) + .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH)-1:0]) ); //assign Y = (partial[n-1] << (n-1)*`DSP_A_MAXWIDTH) + partial_sum[n-2]; assign Y = { - partial[n-1][A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH:0] + partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH):0] + partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_A_MAXWIDTH)], partial_sum[n-2][((n-1)*`DSP_A_MAXWIDTH)-1:0] }; @@ -137,19 +139,21 @@ module \$__mul_gen (A, B, Y); localparam n = n_floored + (n_floored*`DSP_B_MAXWIDTH < B_WIDTH ? 1 : 0); wire [A_WIDTH+`DSP_B_MAXWIDTH-1:0] partial [n-1:1]; wire [Y_WIDTH-1:0] partial_sum [n-2:0]; + localparam int_yw = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH); \$__mul_gen #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), - .Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH) + .Y_WIDTH(int_yw) ) mul_first ( .A(A), .B(B[`DSP_B_MAXWIDTH-1:0]), - .Y(partial_sum[0][A_WIDTH+`DSP_B_MAXWIDTH-1:0]) + .Y(partial_sum[0][int_yw-1:0]) ); - assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0; + if (Y_WIDTH > int_yw) + assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0; for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( @@ -157,11 +161,11 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), - .Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH) + .Y_WIDTH(int_yw) ) mul ( .A(A), .B(B[(i+1)*`DSP_B_MAXWIDTH-1:i*`DSP_B_MAXWIDTH]), - .Y(partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:0]) + .Y(partial[i][int_yw-1:0]) ); //assign partial_sum[i] = (partial[i] << i*`DSP_B_MAXWIDTH) + partial_sum[i-1]; // was: @@ -170,7 +174,7 @@ module \$__mul_gen (A, B, Y); // partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)], // partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0] assign partial_sum[i] = { - partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:0] + partial[i][int_yw-1:0] + partial_sum[i-1][Y_WIDTH-1:(i*`DSP_B_MAXWIDTH)], partial_sum[i-1][(i*`DSP_B_MAXWIDTH)-1:0] }; @@ -181,11 +185,11 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-(n-1)*`DSP_B_MAXWIDTH), - .Y_WIDTH(A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH) + .Y_WIDTH(`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH)) ) mul_last ( .A(A), .B(B[B_WIDTH-1:(n-1)*`DSP_B_MAXWIDTH]), - .Y(partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0]) + .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH)-1:0]) ); // AMD: this came comment out -- looks closer to right answer //assign Y = (partial[n-1] << (n-1)*`DSP_B_MAXWIDTH) + partial_sum[n-2]; @@ -195,7 +199,7 @@ module \$__mul_gen (A, B, Y); // partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)], // partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0] assign Y = { - partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0] + partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH)-1:0] + partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_B_MAXWIDTH)], partial_sum[n-2][((n-1)*`DSP_B_MAXWIDTH)-1:0] }; -- cgit v1.2.3 From 0b6d47f8bfe3117817398a7a84a2d93dd339335b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Jul 2019 15:55:13 -0700 Subject: Add DSP_{A,B}_SIGNEDONLY macro --- techlibs/common/mul2dsp.v | 51 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 40 insertions(+), 11 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 6f2281c0a..258ddf021 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -3,24 +3,25 @@ // revised by Andre DeHon // further revised by David Shah `ifndef DSP_A_MAXWIDTH -`define DSP_A_MAXWIDTH 18 +$error("Macro DSP_A_MAXWIDTH must be defined"); `endif -`ifndef DSP_A_MAXWIDTH -`define DSP_B_MAXWIDTH 25 +`ifndef DSP_A_SIGNEDONLY +`define DSP_A_SIGNEDONLY 0 `endif - -`ifndef ADDER_MINWIDTH -`define ADDER_MINWIDTH AAA +`ifndef DSP_B_MAXWIDTH +$error("Macro DSP_B_MAXWIDTH must be defined"); +`endif +`ifndef DSP_B_SIGNEDONLY +`define DSP_B_SIGNEDONLY 0 `endif `ifndef DSP_NAME -`define DSP_NAME M18x25 +$error("Macro DSP_NAME must be defined"); `endif `define MAX(a,b) (a > b ? a : b) `define MIN(a,b) (a < b ? a : b) -(* techmap_celltype = "$mul" *) module \$mul (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; @@ -33,14 +34,42 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (A_WIDTH >= B_WIDTH) + if (`DSP_A_SIGNEDONLY && !A_SIGNED) begin + wire dummy; + \$mul #( + .A_SIGNED(1), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH+1), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH+1) + ) _TECHMAP_REPLACE_ ( + .A({1'b0, A}), + .B(B), + .Y({dummy, Y}) + ); + end + else if (`DSP_B_SIGNEDONLY && !B_SIGNED) begin + wire dummy; + \$mul #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(1), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH+1), + .Y_WIDTH(Y_WIDTH+1) + ) _TECHMAP_REPLACE_ ( + .A(A), + .B({1'b0, B}), + .Y({dummy, Y}) + ); + end + else if (A_WIDTH >= B_WIDTH) \$__mul_gen #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH) - ) mul_slice ( + ) _TECHMAP_REPLACE_ ( .A(A), .B(B), .Y(Y) @@ -52,7 +81,7 @@ module \$mul (A, B, Y); .A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH) - ) mul_slice ( + ) _TECHMAP_REPLACE_ ( .A(B), .B(A), .Y(Y) -- cgit v1.2.3 From 1b62b82e05ef5405d8ddff211f623d90d848a9ca Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 17 Jul 2019 11:34:18 -0700 Subject: A_SIGNED == B_SIGNED so flip both --- techlibs/common/mul2dsp.v | 33 ++++++++++++--------------------- 1 file changed, 12 insertions(+), 21 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 258ddf021..d19599620 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -34,31 +34,22 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (`DSP_A_SIGNEDONLY && !A_SIGNED) begin - wire dummy; + localparam add_sign_A = `DSP_A_SIGNEDONLY && !A_SIGNED; + localparam add_sign_B = `DSP_B_SIGNEDONLY && !B_SIGNED; + if (add_sign_A || add_sign_B) begin + if (add_sign_A && add_sign_B) + wire [1:0] dummy; + else + wire dummy; \$mul #( .A_SIGNED(1), - .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH+1), - .B_WIDTH(B_WIDTH), - .Y_WIDTH(Y_WIDTH+1) - ) _TECHMAP_REPLACE_ ( - .A({1'b0, A}), - .B(B), - .Y({dummy, Y}) - ); - end - else if (`DSP_B_SIGNEDONLY && !B_SIGNED) begin - wire dummy; - \$mul #( - .A_SIGNED(A_SIGNED), .B_SIGNED(1), - .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH+1), - .Y_WIDTH(Y_WIDTH+1) + .A_WIDTH(A_WIDTH + (add_sign_A ? 1 : 0)), + .B_WIDTH(B_WIDTH + (add_sign_B ? 1 : 0)), + .Y_WIDTH(Y_WIDTH + (add_sign_A ? 1 : 0) + (add_sign_B ? 1 : 0)) ) _TECHMAP_REPLACE_ ( - .A(A), - .B({1'b0, B}), + .A(add_sign_A ? {1'b0, A} : A), + .B(add_sign_B ? {1'b0, B} : B), .Y({dummy, Y}) ); end -- cgit v1.2.3 From 8dca8d486e945eb5883e6757f711011ed23aa5ba Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 17 Jul 2019 12:44:52 -0700 Subject: Fix mul2dsp signedness --- techlibs/common/mul2dsp.v | 80 ++++++++++++++++++++++------------------------- 1 file changed, 38 insertions(+), 42 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index d19599620..7344bc5fe 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -34,49 +34,45 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - localparam add_sign_A = `DSP_A_SIGNEDONLY && !A_SIGNED; - localparam add_sign_B = `DSP_B_SIGNEDONLY && !B_SIGNED; - if (add_sign_A || add_sign_B) begin - if (add_sign_A && add_sign_B) - wire [1:0] dummy; - else - wire dummy; - \$mul #( - .A_SIGNED(1), - .B_SIGNED(1), - .A_WIDTH(A_WIDTH + (add_sign_A ? 1 : 0)), - .B_WIDTH(B_WIDTH + (add_sign_B ? 1 : 0)), - .Y_WIDTH(Y_WIDTH + (add_sign_A ? 1 : 0) + (add_sign_B ? 1 : 0)) - ) _TECHMAP_REPLACE_ ( - .A(add_sign_A ? {1'b0, A} : A), - .B(add_sign_B ? {1'b0, B} : B), - .Y({dummy, Y}) - ); + if (`DSP_A_SIGNEDONLY && `DSP_B_SIGNEDONLY && !A_SIGNED) begin + wire [1:0] dummy; + \$mul #( + .A_SIGNED(1), + .B_SIGNED(1), + .A_WIDTH(A_WIDTH + 1), + .B_WIDTH(B_WIDTH + 1), + .Y_WIDTH(Y_WIDTH + 2) + ) _TECHMAP_REPLACE_ ( + .A({1'b0, A}), + .B({1'b0, B}), + .Y({dummy, Y}) + ); end - else if (A_WIDTH >= B_WIDTH) - \$__mul_gen #( - .A_SIGNED(A_SIGNED), - .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH), - .Y_WIDTH(Y_WIDTH) - ) _TECHMAP_REPLACE_ ( - .A(A), - .B(B), - .Y(Y) - ); - else - \$__mul_gen #( - .A_SIGNED(B_SIGNED), - .B_SIGNED(A_SIGNED), - .A_WIDTH(B_WIDTH), - .B_WIDTH(A_WIDTH), - .Y_WIDTH(Y_WIDTH) - ) _TECHMAP_REPLACE_ ( - .A(B), - .B(A), - .Y(Y) - ); + // NB: A_SIGNED == B_SIGNED == 0 from here + else if (A_WIDTH >= B_WIDTH) + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A(A), + .B(B), + .Y(Y) + ); + else + \$__mul_gen #( + .A_SIGNED(B_SIGNED), + .B_SIGNED(A_SIGNED), + .A_WIDTH(B_WIDTH), + .B_WIDTH(A_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A(B), + .B(A), + .Y(Y) + ); endgenerate endmodule -- cgit v1.2.3 From 16b0ccf04ca83d76f9bd182e125dd75fa838753a Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 18 Jul 2019 11:33:37 +0100 Subject: mul2dsp: Lower partial products always have unsigned inputs Signed-off-by: David Shah --- techlibs/common/mul2dsp.v | 72 +++++++++++++++++++++++++++-------------------- 1 file changed, 41 insertions(+), 31 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 7344bc5fe..31469ddeb 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -92,20 +92,25 @@ module \$__mul_gen (A, B, Y); genvar i; generate if (A_WIDTH > `DSP_A_MAXWIDTH) begin - localparam n_floored = A_WIDTH/`DSP_A_MAXWIDTH; - localparam n = n_floored + (n_floored*`DSP_A_MAXWIDTH < A_WIDTH ? 1 : 0); +`ifdef DSP_A_SIGNEDONLY + localparam sign_headroom = 1; +`else + localparam sign_headroom = 0; +`endif + localparam n_floored = A_WIDTH/(`DSP_A_MAXWIDTH - sign_headroom); + localparam n = n_floored + (n_floored*(`DSP_A_MAXWIDTH - sign_headroom) < A_WIDTH ? 1 : 0); wire [`DSP_A_MAXWIDTH+B_WIDTH-1:0] partial [n-1:1]; wire [Y_WIDTH-1:0] partial_sum [n-2:0]; localparam int_yw = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); \$__mul_gen #( - .A_SIGNED(A_SIGNED), + .A_SIGNED(0), .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(int_yw) ) mul_slice_first ( - .A(A[`DSP_A_MAXWIDTH-1:0]), + .A({{sign_headroom{1'b0}}, A[`DSP_A_MAXWIDTH-sign_headroom-1:0]}), .B(B), .Y(partial_sum[0][int_yw-1:0]) ); @@ -114,73 +119,78 @@ module \$__mul_gen (A, B, Y); for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( - .A_SIGNED(A_SIGNED), + .A_SIGNED(0), .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(int_yw) ) mul_slice ( - .A(A[(i+1)*`DSP_A_MAXWIDTH-1:i*`DSP_A_MAXWIDTH]), + .A({{sign_headroom{1'b0}}, A[(i+1)*(`DSP_A_MAXWIDTH-sign_headroom)-1:i*(`DSP_A_MAXWIDTH-sign_headroom)]}), .B(B), .Y(partial[i][int_yw-1:0]) ); //assign partial_sum[i] = (partial[i] << i*`DSP_A_MAXWIDTH) + partial_sum[i-1]; assign partial_sum[i] = { partial[i][int_yw-1:0] - + partial_sum[i-1][Y_WIDTH-1:(i*`DSP_A_MAXWIDTH)], - partial_sum[i-1][(i*`DSP_A_MAXWIDTH)-1:0] + + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_A_MAXWIDTH-sign_headroom))], + partial_sum[i-1][(i*(`DSP_A_MAXWIDTH-sign_headroom))-1:0] }; end \$__mul_gen #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH), + .A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)), .B_WIDTH(B_WIDTH), - .Y_WIDTH(`MIN(Y_WIDTH, A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH)), + .Y_WIDTH(`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH)), ) mul_slice_last ( - .A(A[A_WIDTH-1:(n-1)*`DSP_A_MAXWIDTH]), + .A(A[A_WIDTH-1:(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]), .B(B), - .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH)-1:0]) + .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH)-1:0]) ); //assign Y = (partial[n-1] << (n-1)*`DSP_A_MAXWIDTH) + partial_sum[n-2]; assign Y = { - partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH):0] - + partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_A_MAXWIDTH)], - partial_sum[n-2][((n-1)*`DSP_A_MAXWIDTH)-1:0] + partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH):0] + + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))], + partial_sum[n-2][((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))-1:0] }; end else if (B_WIDTH > `DSP_B_MAXWIDTH) begin - localparam n_floored = B_WIDTH/`DSP_B_MAXWIDTH; - localparam n = n_floored + (n_floored*`DSP_B_MAXWIDTH < B_WIDTH ? 1 : 0); +`ifdef DSP_B_SIGNEDONLY + localparam sign_headroom = 1; +`else + localparam sign_headroom = 0; +`endif + localparam n_floored = B_WIDTH/(`DSP_B_MAXWIDTH - sign_headroom); + localparam n = n_floored + (n_floored*(`DSP_B_MAXWIDTH - sign_headroom) < B_WIDTH ? 1 : 0); wire [A_WIDTH+`DSP_B_MAXWIDTH-1:0] partial [n-1:1]; wire [Y_WIDTH-1:0] partial_sum [n-2:0]; localparam int_yw = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH); \$__mul_gen #( .A_SIGNED(A_SIGNED), - .B_SIGNED(B_SIGNED), + .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), .Y_WIDTH(int_yw) ) mul_first ( .A(A), - .B(B[`DSP_B_MAXWIDTH-1:0]), + .B({{sign_headroom{1'b0}}, B[(`DSP_B_MAXWIDTH - sign_headroom)-1:0]}), .Y(partial_sum[0][int_yw-1:0]) ); if (Y_WIDTH > int_yw) - assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0; + assign partial_sum[0][Y_WIDTH-1:int_yw]=0; for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( .A_SIGNED(A_SIGNED), - .B_SIGNED(B_SIGNED), + .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), .Y_WIDTH(int_yw) ) mul ( .A(A), - .B(B[(i+1)*`DSP_B_MAXWIDTH-1:i*`DSP_B_MAXWIDTH]), + .B({{sign_headroom{1'b0}}, B[(i+1)*(`DSP_B_MAXWIDTH - sign_headroom)-1:i*(`DSP_B_MAXWIDTH - sign_headroom)]}), .Y(partial[i][int_yw-1:0]) ); //assign partial_sum[i] = (partial[i] << i*`DSP_B_MAXWIDTH) + partial_sum[i-1]; @@ -191,8 +201,8 @@ module \$__mul_gen (A, B, Y); // partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0] assign partial_sum[i] = { partial[i][int_yw-1:0] - + partial_sum[i-1][Y_WIDTH-1:(i*`DSP_B_MAXWIDTH)], - partial_sum[i-1][(i*`DSP_B_MAXWIDTH)-1:0] + + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_B_MAXWIDTH - sign_headroom))], + partial_sum[i-1][(i*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] }; end @@ -200,12 +210,12 @@ module \$__mul_gen (A, B, Y); .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH-(n-1)*`DSP_B_MAXWIDTH), - .Y_WIDTH(`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH)) + .B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)), + .Y_WIDTH(`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))) ) mul_last ( .A(A), - .B(B[B_WIDTH-1:(n-1)*`DSP_B_MAXWIDTH]), - .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH)-1:0]) + .B(B[B_WIDTH-1:(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)]), + .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0]) ); // AMD: this came comment out -- looks closer to right answer //assign Y = (partial[n-1] << (n-1)*`DSP_B_MAXWIDTH) + partial_sum[n-2]; @@ -215,9 +225,9 @@ module \$__mul_gen (A, B, Y); // partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)], // partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0] assign Y = { - partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH)-1:0] - + partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_B_MAXWIDTH)], - partial_sum[n-2][((n-1)*`DSP_B_MAXWIDTH)-1:0] + partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] + + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))], + partial_sum[n-2][((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] }; end else begin -- cgit v1.2.3 From d5cd2c80be95857cfd30d50081d6c87415e9169a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 09:20:48 -0700 Subject: Cleanup --- techlibs/common/mul2dsp.v | 128 +++++++++++++++++++++------------------------- 1 file changed, 58 insertions(+), 70 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 31469ddeb..9da778ace 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -97,25 +97,23 @@ module \$__mul_gen (A, B, Y); `else localparam sign_headroom = 0; `endif - localparam n_floored = A_WIDTH/(`DSP_A_MAXWIDTH - sign_headroom); - localparam n = n_floored + (n_floored*(`DSP_A_MAXWIDTH - sign_headroom) < A_WIDTH ? 1 : 0); - wire [`DSP_A_MAXWIDTH+B_WIDTH-1:0] partial [n-1:1]; + localparam n = (A_WIDTH + `DSP_A_MAXWIDTH - sign_headroom - 1)/(`DSP_A_MAXWIDTH - sign_headroom); + localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); + wire [partial_Y_WIDTH-1:0] partial [n-1:1]; wire [Y_WIDTH-1:0] partial_sum [n-2:0]; - localparam int_yw = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); \$__mul_gen #( .A_SIGNED(0), .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), - .Y_WIDTH(int_yw) + .Y_WIDTH(partial_Y_WIDTH) ) mul_slice_first ( .A({{sign_headroom{1'b0}}, A[`DSP_A_MAXWIDTH-sign_headroom-1:0]}), .B(B), - .Y(partial_sum[0][int_yw-1:0]) + .Y(partial[0]) ); - if (Y_WIDTH > int_yw) - assign partial_sum[0][Y_WIDTH-1:int_yw]=0; + assign partial_sum[0] = partial[0]; for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( @@ -123,18 +121,18 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), - .Y_WIDTH(int_yw) + .Y_WIDTH(partial_Y_WIDTH) ) mul_slice ( - .A({{sign_headroom{1'b0}}, A[(i+1)*(`DSP_A_MAXWIDTH-sign_headroom)-1:i*(`DSP_A_MAXWIDTH-sign_headroom)]}), + .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH-sign_headroom) +: `DSP_A_MAXWIDTH-sign_headroom]}), .B(B), - .Y(partial[i][int_yw-1:0]) + .Y(partial[i]) ); - //assign partial_sum[i] = (partial[i] << i*`DSP_A_MAXWIDTH) + partial_sum[i-1]; - assign partial_sum[i] = { - partial[i][int_yw-1:0] - + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_A_MAXWIDTH-sign_headroom))], - partial_sum[i-1][(i*(`DSP_A_MAXWIDTH-sign_headroom))-1:0] - }; + assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; + //assign partial_sum[i] = { + // partial[i][partial_Y_WIDTH-1:0] + // + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_A_MAXWIDTH-sign_headroom))], + // partial_sum[i-1][(i*(`DSP_A_MAXWIDTH-sign_headroom))-1:0] + //}; end \$__mul_gen #( @@ -148,12 +146,12 @@ module \$__mul_gen (A, B, Y); .B(B), .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH)-1:0]) ); - //assign Y = (partial[n-1] << (n-1)*`DSP_A_MAXWIDTH) + partial_sum[n-2]; - assign Y = { - partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH):0] - + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))], - partial_sum[n-2][((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))-1:0] - }; + assign Y = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; + //assign Y = { + // partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH):0] + // + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))], + // partial_sum[n-2][((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))-1:0] + //}; end else if (B_WIDTH > `DSP_B_MAXWIDTH) begin `ifdef DSP_B_SIGNEDONLY @@ -161,25 +159,23 @@ module \$__mul_gen (A, B, Y); `else localparam sign_headroom = 0; `endif - localparam n_floored = B_WIDTH/(`DSP_B_MAXWIDTH - sign_headroom); - localparam n = n_floored + (n_floored*(`DSP_B_MAXWIDTH - sign_headroom) < B_WIDTH ? 1 : 0); - wire [A_WIDTH+`DSP_B_MAXWIDTH-1:0] partial [n-1:1]; + localparam n = (B_WIDTH + `DSP_B_MAXWIDTH - sign_headroom - 1)/(`DSP_B_MAXWIDTH - sign_headroom); + localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH); + wire [partial_Y_WIDTH-1:0] partial [n-1:1]; wire [Y_WIDTH-1:0] partial_sum [n-2:0]; - localparam int_yw = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH); \$__mul_gen #( .A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), - .Y_WIDTH(int_yw) + .Y_WIDTH(partial_Y_WIDTH) ) mul_first ( .A(A), - .B({{sign_headroom{1'b0}}, B[(`DSP_B_MAXWIDTH - sign_headroom)-1:0]}), - .Y(partial_sum[0][int_yw-1:0]) + .B({{sign_headroom{1'b0}}, B[`DSP_B_MAXWIDTH-sign_headroom-1:0]}), + .Y(partial[0]) ); - if (Y_WIDTH > int_yw) - assign partial_sum[0][Y_WIDTH-1:int_yw]=0; + assign partial_sum[0] = partial[0]; for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( @@ -187,23 +183,23 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), - .Y_WIDTH(int_yw) + .Y_WIDTH(partial_Y_WIDTH) ) mul ( .A(A), - .B({{sign_headroom{1'b0}}, B[(i+1)*(`DSP_B_MAXWIDTH - sign_headroom)-1:i*(`DSP_B_MAXWIDTH - sign_headroom)]}), - .Y(partial[i][int_yw-1:0]) + .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}), + .Y(partial[i]) ); - //assign partial_sum[i] = (partial[i] << i*`DSP_B_MAXWIDTH) + partial_sum[i-1]; - // was: + assign partial_sum[i] = (partial[i] <<< i*(`DSP_B_MAXWIDTH - sign_headroom)) + partial_sum[i-1]; + //// was: + ////assign partial_sum[i] = { + //// partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], + //// partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)], + //// partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0] //assign partial_sum[i] = { - // partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], - // partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)], - // partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0] - assign partial_sum[i] = { - partial[i][int_yw-1:0] - + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_B_MAXWIDTH - sign_headroom))], - partial_sum[i-1][(i*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] - }; + // partial[i][partial_Y_WIDTH-1:0] + // + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_B_MAXWIDTH - sign_headroom))], + // partial_sum[i-1][(i*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] + //}; end \$__mul_gen #( @@ -217,36 +213,28 @@ module \$__mul_gen (A, B, Y); .B(B[B_WIDTH-1:(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)]), .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0]) ); - // AMD: this came comment out -- looks closer to right answer - //assign Y = (partial[n-1] << (n-1)*`DSP_B_MAXWIDTH) + partial_sum[n-2]; - // was (looks broken) + assign Y = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH - sign_headroom)) + partial_sum[n-2]; + //// was (looks broken) + ////assign Y = { + //// partial[n-1][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], + //// partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)], + //// partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0] //assign Y = { - // partial[n-1][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], - // partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)], - // partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0] - assign Y = { - partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] - + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))], - partial_sum[n-2][((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] - }; + // partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] + // + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))], + // partial_sum[n-2][((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] + //}; end else begin - wire [A_WIDTH+B_WIDTH-1:0] out; - wire [(`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)-(A_WIDTH+B_WIDTH)-1:0] dummy; - wire Asign, Bsign; - assign Asign = (A_SIGNED ? A[A_WIDTH-1] : 1'b0); - assign Bsign = (B_SIGNED ? B[B_WIDTH-1] : 1'b0); + (* keep *) wire [Y_WIDTH-1:0] Yunsigned; + wire signed [`DSP_A_MAXWIDTH-1:0] Asigned = $signed(A); + wire signed [`DSP_A_MAXWIDTH-1:0] Bsigned = $signed(B); `DSP_NAME _TECHMAP_REPLACE_ ( - .A({ {{`DSP_A_MAXWIDTH-A_WIDTH}{Asign}}, A }), - .B({ {{`DSP_B_MAXWIDTH-B_WIDTH}{Bsign}}, B }), - .Y({dummy, out}) + .A(Asigned), + .B(Bsigned), + .Y(Yunsigned) ); - if (Y_WIDTH < A_WIDTH+B_WIDTH) - assign Y = out[Y_WIDTH-1:0]; - else begin - wire Ysign = (A_SIGNED || B_SIGNED ? out[A_WIDTH+B_WIDTH-1] : 1'b0); - assign Y = { {{Y_WIDTH-(A_WIDTH+B_WIDTH)}{Ysign}}, out[A_WIDTH+B_WIDTH-1:0] }; - end + assign Y = $signed(Yunsigned[A_WIDTH+B_WIDTH-1:0]); end endgenerate endmodule -- cgit v1.2.3 From 2024357f32b3a5ee562501f66b16c30d9554aa4b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 10:53:18 -0700 Subject: Working for unsigned --- techlibs/common/mul2dsp.v | 80 +++++++++++++++++------------------------------ 1 file changed, 28 insertions(+), 52 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 9da778ace..4af3b871b 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -34,7 +34,7 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (`DSP_A_SIGNEDONLY && `DSP_B_SIGNEDONLY && !A_SIGNED) begin + if (`DSP_SIGNEDONLY && !A_SIGNED) begin wire [1:0] dummy; \$mul #( .A_SIGNED(1), @@ -89,22 +89,23 @@ module \$__mul_gen (A, B, Y); wire [1023:0] _TECHMAP_DO_ = "proc; clean"; +`ifdef DSP_SIGNEDONLY + localparam sign_headroom = 1; +`else + localparam sign_headroom = 0; +`endif + genvar i; generate if (A_WIDTH > `DSP_A_MAXWIDTH) begin -`ifdef DSP_A_SIGNEDONLY - localparam sign_headroom = 1; -`else - localparam sign_headroom = 0; -`endif localparam n = (A_WIDTH + `DSP_A_MAXWIDTH - sign_headroom - 1)/(`DSP_A_MAXWIDTH - sign_headroom); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); wire [partial_Y_WIDTH-1:0] partial [n-1:1]; - wire [Y_WIDTH-1:0] partial_sum [n-2:0]; + wire [Y_WIDTH-1:0] partial_sum [n-1:0]; \$__mul_gen #( .A_SIGNED(0), - .B_SIGNED(B_SIGNED), + .B_SIGNED(0), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(partial_Y_WIDTH) @@ -118,7 +119,7 @@ module \$__mul_gen (A, B, Y); for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( .A_SIGNED(0), - .B_SIGNED(B_SIGNED), + .B_SIGNED(0), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(partial_Y_WIDTH) @@ -128,11 +129,6 @@ module \$__mul_gen (A, B, Y); .Y(partial[i]) ); assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; - //assign partial_sum[i] = { - // partial[i][partial_Y_WIDTH-1:0] - // + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_A_MAXWIDTH-sign_headroom))], - // partial_sum[i-1][(i*(`DSP_A_MAXWIDTH-sign_headroom))-1:0] - //}; end \$__mul_gen #( @@ -140,18 +136,13 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)), .B_WIDTH(B_WIDTH), - .Y_WIDTH(`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH)), + .Y_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom) + B_WIDTH), ) mul_slice_last ( .A(A[A_WIDTH-1:(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]), .B(B), - .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH)-1:0]) + .Y(partial[n-1]) ); assign Y = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; - //assign Y = { - // partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH):0] - // + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))], - // partial_sum[n-2][((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))-1:0] - //}; end else if (B_WIDTH > `DSP_B_MAXWIDTH) begin `ifdef DSP_B_SIGNEDONLY @@ -162,7 +153,7 @@ module \$__mul_gen (A, B, Y); localparam n = (B_WIDTH + `DSP_B_MAXWIDTH - sign_headroom - 1)/(`DSP_B_MAXWIDTH - sign_headroom); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH); wire [partial_Y_WIDTH-1:0] partial [n-1:1]; - wire [Y_WIDTH-1:0] partial_sum [n-2:0]; + wire [Y_WIDTH-1:0] partial_sum [n-1:0]; \$__mul_gen #( .A_SIGNED(A_SIGNED), @@ -189,17 +180,7 @@ module \$__mul_gen (A, B, Y); .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}), .Y(partial[i]) ); - assign partial_sum[i] = (partial[i] <<< i*(`DSP_B_MAXWIDTH - sign_headroom)) + partial_sum[i-1]; - //// was: - ////assign partial_sum[i] = { - //// partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], - //// partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)], - //// partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0] - //assign partial_sum[i] = { - // partial[i][partial_Y_WIDTH-1:0] - // + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_B_MAXWIDTH - sign_headroom))], - // partial_sum[i-1][(i*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] - //}; + assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH - sign_headroom)) + partial_sum[i-1]; end \$__mul_gen #( @@ -207,34 +188,29 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)), - .Y_WIDTH(`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))) + .Y_WIDTH(A_WIDTH + B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)) ) mul_last ( .A(A), .B(B[B_WIDTH-1:(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)]), - .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0]) + .Y(partial[n-1]) ); assign Y = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH - sign_headroom)) + partial_sum[n-2]; - //// was (looks broken) - ////assign Y = { - //// partial[n-1][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], - //// partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)], - //// partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0] - //assign Y = { - // partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] - // + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))], - // partial_sum[n-2][((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] - //}; end else begin - (* keep *) wire [Y_WIDTH-1:0] Yunsigned; - wire signed [`DSP_A_MAXWIDTH-1:0] Asigned = $signed(A); - wire signed [`DSP_A_MAXWIDTH-1:0] Bsigned = $signed(B); + if (A_SIGNED) + wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A); + else + wire [`DSP_A_MAXWIDTH-1:0] Aext = A; + if (B_SIGNED) + wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B); + else + wire [`DSP_B_MAXWIDTH-1:0] Bext = B; + `DSP_NAME _TECHMAP_REPLACE_ ( - .A(Asigned), - .B(Bsigned), - .Y(Yunsigned) + .A(Aext), + .B(Bext), + .Y(Y) ); - assign Y = $signed(Yunsigned[A_WIDTH+B_WIDTH-1:0]); end endgenerate endmodule -- cgit v1.2.3 From 8326af5418205e51452e0cced8d2253afe730e76 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 13:11:26 -0700 Subject: Fix signed multiplier decomposition --- techlibs/common/mul2dsp.v | 65 ++++++++++++++++++++++++++--------------------- 1 file changed, 36 insertions(+), 29 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 4af3b871b..2819c939e 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -5,14 +5,11 @@ `ifndef DSP_A_MAXWIDTH $error("Macro DSP_A_MAXWIDTH must be defined"); `endif -`ifndef DSP_A_SIGNEDONLY -`define DSP_A_SIGNEDONLY 0 -`endif `ifndef DSP_B_MAXWIDTH $error("Macro DSP_B_MAXWIDTH must be defined"); `endif -`ifndef DSP_B_SIGNEDONLY -`define DSP_B_SIGNEDONLY 0 +`ifndef DSP_SIGNEDONLY +`define DSP_SIGNEDONLY 0 `endif `ifndef DSP_NAME @@ -34,7 +31,9 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (`DSP_SIGNEDONLY && !A_SIGNED) begin + if (A_SIGNED != B_SIGNED) + wire _TECHMAP_FAIL_ = 1; + else if (`DSP_SIGNEDONLY && !A_SIGNED) begin wire [1:0] dummy; \$mul #( .A_SIGNED(1), @@ -98,19 +97,25 @@ module \$__mul_gen (A, B, Y); genvar i; generate if (A_WIDTH > `DSP_A_MAXWIDTH) begin - localparam n = (A_WIDTH + `DSP_A_MAXWIDTH - sign_headroom - 1)/(`DSP_A_MAXWIDTH - sign_headroom); + localparam n = (A_WIDTH+`DSP_A_MAXWIDTH-sign_headroom-1) / (`DSP_A_MAXWIDTH-sign_headroom); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); - wire [partial_Y_WIDTH-1:0] partial [n-1:1]; - wire [Y_WIDTH-1:0] partial_sum [n-1:0]; + if (A_SIGNED && B_SIGNED) begin + wire signed [partial_Y_WIDTH-1:0] partial [n-1:0]; + wire signed [Y_WIDTH-1:0] partial_sum [n-1:0]; + end + else begin + wire [partial_Y_WIDTH-1:0] partial [n-1:0]; + wire [Y_WIDTH-1:0] partial_sum [n-1:0]; + end \$__mul_gen #( .A_SIGNED(0), - .B_SIGNED(0), + .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(partial_Y_WIDTH) ) mul_slice_first ( - .A({{sign_headroom{1'b0}}, A[`DSP_A_MAXWIDTH-sign_headroom-1:0]}), + .A({{sign_headroom{1'b0}}, A[`DSP_A_MAXWIDTH-sign_headroom-1 : 0]}), .B(B), .Y(partial[0]) ); @@ -119,7 +124,7 @@ module \$__mul_gen (A, B, Y); for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( .A_SIGNED(0), - .B_SIGNED(0), + .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(partial_Y_WIDTH) @@ -136,24 +141,26 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)), .B_WIDTH(B_WIDTH), - .Y_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom) + B_WIDTH), + .Y_WIDTH(partial_Y_WIDTH) ) mul_slice_last ( - .A(A[A_WIDTH-1:(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]), + .A(A[A_WIDTH-1 : (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]), .B(B), .Y(partial[n-1]) ); - assign Y = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; + assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; + assign Y = partial_sum[n-1]; end else if (B_WIDTH > `DSP_B_MAXWIDTH) begin -`ifdef DSP_B_SIGNEDONLY - localparam sign_headroom = 1; -`else - localparam sign_headroom = 0; -`endif - localparam n = (B_WIDTH + `DSP_B_MAXWIDTH - sign_headroom - 1)/(`DSP_B_MAXWIDTH - sign_headroom); + localparam n = (B_WIDTH+`DSP_B_MAXWIDTH-sign_headroom-1) / (`DSP_B_MAXWIDTH-sign_headroom); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH); - wire [partial_Y_WIDTH-1:0] partial [n-1:1]; - wire [Y_WIDTH-1:0] partial_sum [n-1:0]; + if (A_SIGNED && B_SIGNED) begin + wire signed [partial_Y_WIDTH-1:0] partial [n-1:0]; + wire signed [Y_WIDTH-1:0] partial_sum [n-1:0]; + end + else begin + wire [partial_Y_WIDTH-1:0] partial [n-1:0]; + wire [Y_WIDTH-1:0] partial_sum [n-1:0]; + end \$__mul_gen #( .A_SIGNED(A_SIGNED), @@ -163,7 +170,7 @@ module \$__mul_gen (A, B, Y); .Y_WIDTH(partial_Y_WIDTH) ) mul_first ( .A(A), - .B({{sign_headroom{1'b0}}, B[`DSP_B_MAXWIDTH-sign_headroom-1:0]}), + .B({{sign_headroom{1'b0}}, B[`DSP_B_MAXWIDTH-sign_headroom-1 : 0]}), .Y(partial[0]) ); assign partial_sum[0] = partial[0]; @@ -180,21 +187,21 @@ module \$__mul_gen (A, B, Y); .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}), .Y(partial[i]) ); - assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH - sign_headroom)) + partial_sum[i-1]; + assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; end \$__mul_gen #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)), - .Y_WIDTH(A_WIDTH + B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)) + .B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom)), + .Y_WIDTH(partial_Y_WIDTH) ) mul_last ( .A(A), - .B(B[B_WIDTH-1:(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)]), + .B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]), .Y(partial[n-1]) ); - assign Y = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH - sign_headroom)) + partial_sum[n-2]; + assign Y = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; end else begin if (A_SIGNED) -- cgit v1.2.3 From e22a7522422ec5f2f6db52d4e9c98d09868ea3e3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 15:21:23 -0700 Subject: Make consistent --- techlibs/common/mul2dsp.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 2819c939e..ee53701ee 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -201,7 +201,8 @@ module \$__mul_gen (A, B, Y); .B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]), .Y(partial[n-1]) ); - assign Y = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; + assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; + assign Y = partial_sum[n-1]; end else begin if (A_SIGNED) -- cgit v1.2.3 From 2339b7fc3732996a217f635d95f1f7400cf43d48 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 15:37:35 -0700 Subject: mul2dsp to create cells that can be interchanged with $mul --- techlibs/common/mul2dsp.v | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index ee53701ee..391b395ff 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -214,7 +214,13 @@ module \$__mul_gen (A, B, Y); else wire [`DSP_B_MAXWIDTH-1:0] Bext = B; - `DSP_NAME _TECHMAP_REPLACE_ ( + `DSP_NAME #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(`DSP_A_MAXWIDTH), + .B_WIDTH(`DSP_B_MAXWIDTH), + .Y_WIDTH(`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH), + ) _TECHMAP_REPLACE_ ( .A(Aext), .B(Bext), .Y(Y) -- cgit v1.2.3 From 15c2a79ab96e280ecd6311cb0b726b348a2b1eb5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 16:04:58 -0700 Subject: Do not define `DSP_SIGNEDONLY macro if no exists --- techlibs/common/mul2dsp.v | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 391b395ff..1f4759929 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -8,9 +8,6 @@ $error("Macro DSP_A_MAXWIDTH must be defined"); `ifndef DSP_B_MAXWIDTH $error("Macro DSP_B_MAXWIDTH must be defined"); `endif -`ifndef DSP_SIGNEDONLY -`define DSP_SIGNEDONLY 0 -`endif `ifndef DSP_NAME $error("Macro DSP_NAME must be defined"); @@ -33,7 +30,8 @@ module \$mul (A, B, Y); generate if (A_SIGNED != B_SIGNED) wire _TECHMAP_FAIL_ = 1; - else if (`DSP_SIGNEDONLY && !A_SIGNED) begin +`ifdef DSP_SIGNEDONLY + else if (!A_SIGNED) begin wire [1:0] dummy; \$mul #( .A_SIGNED(1), @@ -47,6 +45,7 @@ module \$mul (A, B, Y); .Y({dummy, Y}) ); end +`endif // NB: A_SIGNED == B_SIGNED == 0 from here else if (A_WIDTH >= B_WIDTH) \$__mul_gen #( -- cgit v1.2.3 From 2168568f43984af2d194c0eab74ad73443f7e84c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 09:16:13 -0700 Subject: Use sign_headroom instead --- techlibs/common/mul2dsp.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 1f4759929..da887d426 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -108,7 +108,7 @@ module \$__mul_gen (A, B, Y); end \$__mul_gen #( - .A_SIGNED(0), + .A_SIGNED(sign_headroom), .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), @@ -122,7 +122,7 @@ module \$__mul_gen (A, B, Y); for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( - .A_SIGNED(0), + .A_SIGNED(sign_headroom), .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), @@ -163,7 +163,7 @@ module \$__mul_gen (A, B, Y); \$__mul_gen #( .A_SIGNED(A_SIGNED), - .B_SIGNED(0), + .B_SIGNED(sign_headroom), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), .Y_WIDTH(partial_Y_WIDTH) @@ -177,7 +177,7 @@ module \$__mul_gen (A, B, Y); for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( .A_SIGNED(A_SIGNED), - .B_SIGNED(0), + .B_SIGNED(sign_headroom), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), .Y_WIDTH(partial_Y_WIDTH) -- cgit v1.2.3 From ca94c2d3c4785c45a2fefdb659e9ff94f2f8c7b3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 10:27:44 -0700 Subject: Fix typo in B --- techlibs/common/mul2dsp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index ee53701ee..da1c7c0c7 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -201,7 +201,7 @@ module \$__mul_gen (A, B, Y); .B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]), .Y(partial[n-1]) ); - assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; + assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; assign Y = partial_sum[n-1]; end else begin -- cgit v1.2.3 From 1d14cec7fd41710aba0bb910a82fa5ca81c4adb0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 11:39:24 -0700 Subject: Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too --- techlibs/common/mul2dsp.v | 96 +++++++++++++++++++++++++++++++++-------------- 1 file changed, 68 insertions(+), 28 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index b6aa02834..aab568c9f 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -28,27 +28,11 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (A_SIGNED != B_SIGNED) + if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1) wire _TECHMAP_FAIL_ = 1; -`ifdef DSP_SIGNEDONLY - else if (!A_SIGNED) begin - wire [1:0] dummy; - \$mul #( - .A_SIGNED(1), - .B_SIGNED(1), - .A_WIDTH(A_WIDTH + 1), - .B_WIDTH(B_WIDTH + 1), - .Y_WIDTH(Y_WIDTH + 2) - ) _TECHMAP_REPLACE_ ( - .A({1'b0, A}), - .B({1'b0, B}), - .Y({dummy, Y}) - ); - end -`endif // NB: A_SIGNED == B_SIGNED == 0 from here else if (A_WIDTH >= B_WIDTH) - \$__mul_gen #( + \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), @@ -60,7 +44,7 @@ module \$mul (A, B, Y); .Y(Y) ); else - \$__mul_gen #( + \$__mul #( .A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), .A_WIDTH(B_WIDTH), @@ -74,7 +58,7 @@ module \$mul (A, B, Y); endgenerate endmodule -module \$__mul_gen (A, B, Y); +module \$__mul (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 1; @@ -95,7 +79,13 @@ module \$__mul_gen (A, B, Y); genvar i; generate - if (A_WIDTH > `DSP_A_MAXWIDTH) begin + if (A_WIDTH <= 1 || B_WIDTH <= 1) + wire _TECHMAP_FAIL_ = 1; +`ifdef DSP_MINWIDTH + else if (A_WIDTH+B_WIDTH < `DSP_MINWIDTH || Y_WIDTH < `DSP_MINWIDTH) + wire _TECHMAP_FAIL_ = 1; +`endif + else if (A_WIDTH > `DSP_A_MAXWIDTH) begin localparam n = (A_WIDTH+`DSP_A_MAXWIDTH-sign_headroom-1) / (`DSP_A_MAXWIDTH-sign_headroom); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); if (A_SIGNED && B_SIGNED) begin @@ -107,7 +97,7 @@ module \$__mul_gen (A, B, Y); wire [Y_WIDTH-1:0] partial_sum [n-1:0]; end - \$__mul_gen #( + \$__mul #( .A_SIGNED(sign_headroom), .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), @@ -121,7 +111,7 @@ module \$__mul_gen (A, B, Y); assign partial_sum[0] = partial[0]; for (i = 1; i < n-1; i=i+1) begin:slice - \$__mul_gen #( + \$__mul #( .A_SIGNED(sign_headroom), .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), @@ -135,7 +125,7 @@ module \$__mul_gen (A, B, Y); assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; end - \$__mul_gen #( + \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)), @@ -161,7 +151,7 @@ module \$__mul_gen (A, B, Y); wire [Y_WIDTH-1:0] partial_sum [n-1:0]; end - \$__mul_gen #( + \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(sign_headroom), .A_WIDTH(A_WIDTH), @@ -175,7 +165,7 @@ module \$__mul_gen (A, B, Y); assign partial_sum[0] = partial[0]; for (i = 1; i < n-1; i=i+1) begin:slice - \$__mul_gen #( + \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(sign_headroom), .A_WIDTH(A_WIDTH), @@ -189,7 +179,7 @@ module \$__mul_gen (A, B, Y); assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; end - \$__mul_gen #( + \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), @@ -218,7 +208,7 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), - .Y_WIDTH(`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH), + .Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)), ) _TECHMAP_REPLACE_ ( .A(Aext), .B(Bext), @@ -228,4 +218,54 @@ module \$__mul_gen (A, B, Y); endgenerate endmodule +(* techmap_celltype = "$__mul" *) +module _90_internal_mul_to_external (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y; + + generate + if (A_SIGNED && !B_SIGNED) + \$mul #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(1), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH+1), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A(A), + .B({1'b0, B}), + .Y(Y) + ); + else if (!A_SIGNED && B_SIGNED) + \$mul #( + .A_SIGNED(1), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH+1), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A({1'b0, A}), + .B(B), + .Y(Y) + ); + else + \$mul #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A(A), + .B(B), + .Y(Y) + ); + endgenerate +endmodule -- cgit v1.2.3 From bba72f03ddd6db370e8fd5afbf14f4f89d0c7e3e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 11:54:26 -0700 Subject: Do not $mul -> $__mul if A and B are less than maxwidth --- techlibs/common/mul2dsp.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index aab568c9f..5444d842a 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -28,7 +28,9 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1) + if (A_SIGNED != B_SIGNED) + wire _TECHMAP_FAIL_ = 1; + else if (A_WIDTH <= `DSP_A_MAXWIDTH && B_WIDTH <= `DSP_B_MAXWIDTH) wire _TECHMAP_FAIL_ = 1; // NB: A_SIGNED == B_SIGNED == 0 from here else if (A_WIDTH >= B_WIDTH) -- cgit v1.2.3 From 595a8f032f1e9db385959f92a4a414a40de291fd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 15:50:13 -0700 Subject: Do not do sign extension in techmap; let packer do it --- techlibs/common/mul2dsp.v | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 5444d842a..70c2c42c6 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -196,24 +196,15 @@ module \$__mul (A, B, Y); assign Y = partial_sum[n-1]; end else begin - if (A_SIGNED) - wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A); - else - wire [`DSP_A_MAXWIDTH-1:0] Aext = A; - if (B_SIGNED) - wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B); - else - wire [`DSP_B_MAXWIDTH-1:0] Bext = B; - `DSP_NAME #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), - .A_WIDTH(`DSP_A_MAXWIDTH), - .B_WIDTH(`DSP_B_MAXWIDTH), - .Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(`MIN(Y_WIDTH,A_WIDTH+B_WIDTH)), ) _TECHMAP_REPLACE_ ( - .A(Aext), - .B(Bext), + .A(A), + .B(B), .Y(Y) ); end -- cgit v1.2.3 From 47fd042b9f8a92df1e1d59042068e7846c4ce808 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 20:20:33 -0700 Subject: Indirection via $__soft_mul --- techlibs/common/mul2dsp.v | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 70c2c42c6..8b1ddefbf 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -28,9 +28,7 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (A_SIGNED != B_SIGNED) - wire _TECHMAP_FAIL_ = 1; - else if (A_WIDTH <= `DSP_A_MAXWIDTH && B_WIDTH <= `DSP_B_MAXWIDTH) + if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1) wire _TECHMAP_FAIL_ = 1; // NB: A_SIGNED == B_SIGNED == 0 from here else if (A_WIDTH >= B_WIDTH) @@ -212,7 +210,7 @@ module \$__mul (A, B, Y); endmodule (* techmap_celltype = "$__mul" *) -module _90_internal_mul_to_external (A, B, Y); +module $__soft_mul (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 1; @@ -223,9 +221,11 @@ module _90_internal_mul_to_external (A, B, Y); input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; + // Indirection necessary since mapping + // back to $mul will cause recursion generate if (A_SIGNED && !B_SIGNED) - \$mul #( + \$__soft__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(1), .A_WIDTH(A_WIDTH), @@ -233,23 +233,23 @@ module _90_internal_mul_to_external (A, B, Y); .Y_WIDTH(Y_WIDTH) ) _TECHMAP_REPLACE_ ( .A(A), - .B({1'b0, B}), + .B({1'b0,B}), .Y(Y) ); else if (!A_SIGNED && B_SIGNED) - \$mul #( + \$__soft_mul #( .A_SIGNED(1), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH) ) _TECHMAP_REPLACE_ ( - .A({1'b0, A}), + .A({1'b0,A}), .B(B), .Y(Y) ); else - \$mul #( + \$__soft_mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), -- cgit v1.2.3 From 3a7aeb028d7680a73c18ec700939cca76aab0433 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 22 Jul 2019 13:01:26 -0700 Subject: Use minimum sized width wires --- techlibs/common/mul2dsp.v | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 8b1ddefbf..cf9eeff6f 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -88,12 +88,15 @@ module \$__mul (A, B, Y); else if (A_WIDTH > `DSP_A_MAXWIDTH) begin localparam n = (A_WIDTH+`DSP_A_MAXWIDTH-sign_headroom-1) / (`DSP_A_MAXWIDTH-sign_headroom); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); + localparam last_Y_WIDTH = `MIN(partial_Y_WIDTH, B_WIDTH+A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)); if (A_SIGNED && B_SIGNED) begin - wire signed [partial_Y_WIDTH-1:0] partial [n-1:0]; + wire signed [partial_Y_WIDTH-1:0] partial [n-2:0]; + wire signed [last_Y_WIDTH-1:0] last_partial; wire signed [Y_WIDTH-1:0] partial_sum [n-1:0]; end else begin wire [partial_Y_WIDTH-1:0] partial [n-1:0]; + wire [last_Y_WIDTH-1:0] last_partial; wire [Y_WIDTH-1:0] partial_sum [n-1:0]; end @@ -130,24 +133,27 @@ module \$__mul (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)), .B_WIDTH(B_WIDTH), - .Y_WIDTH(partial_Y_WIDTH) + .Y_WIDTH(last_Y_WIDTH) ) mul_slice_last ( .A(A[A_WIDTH-1 : (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]), .B(B), - .Y(partial[n-1]) + .Y(last_partial) ); - assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; + assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; assign Y = partial_sum[n-1]; end else if (B_WIDTH > `DSP_B_MAXWIDTH) begin localparam n = (B_WIDTH+`DSP_B_MAXWIDTH-sign_headroom-1) / (`DSP_B_MAXWIDTH-sign_headroom); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH); + localparam last_Y_WIDTH = `MIN(partial_Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom)); if (A_SIGNED && B_SIGNED) begin - wire signed [partial_Y_WIDTH-1:0] partial [n-1:0]; + wire signed [partial_Y_WIDTH-1:0] partial [n-2:0]; + wire signed [last_Y_WIDTH-1:0] last_partial; wire signed [Y_WIDTH-1:0] partial_sum [n-1:0]; end else begin wire [partial_Y_WIDTH-1:0] partial [n-1:0]; + wire [last_Y_WIDTH-1:0] last_partial; wire [Y_WIDTH-1:0] partial_sum [n-1:0]; end @@ -188,9 +194,9 @@ module \$__mul (A, B, Y); ) mul_last ( .A(A), .B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]), - .Y(partial[n-1]) + .Y(last_partial) ); - assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; + assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; assign Y = partial_sum[n-1]; end else begin -- cgit v1.2.3 From 151c5c96c0a85a1b69fc7824949ed89d70667059 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 23 Jul 2019 15:05:20 -0700 Subject: Typo for Y_WIDTH --- techlibs/common/mul2dsp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index cf9eeff6f..06ae3fc04 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -190,7 +190,7 @@ module \$__mul (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom)), - .Y_WIDTH(partial_Y_WIDTH) + .Y_WIDTH(last_Y_WIDTH) ) mul_last ( .A(A), .B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]), -- cgit v1.2.3 From c39ccc65e9ba79aafa6ebd5c3abe9faf7d465a8f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 24 Jul 2019 10:49:09 -0700 Subject: Add copyright header, comment on cascade --- techlibs/common/mul2dsp.v | 38 ++++++++++++++++++++++++++++++++++---- 1 file changed, 34 insertions(+), 4 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 06ae3fc04..a8c2dcccc 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -1,7 +1,31 @@ -// From Eddie Hung -// extracted from: https://github.com/eddiehung/vtr-with-yosys/blob/vtr7-with-yosys/vtr_flow/misc/yosys_models.v#L220 -// revised by Andre DeHon -// further revised by David Shah +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * 2019 Eddie Hung + * 2019 David Shah + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * --- + * + * Tech-mapping rules for decomposing arbitrarily-sized $mul cells + * into an equivalent collection of smaller `DSP_NAME cells (with the + * same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached + * to $shl and $add cells. + * + */ + `ifndef DSP_A_MAXWIDTH $error("Macro DSP_A_MAXWIDTH must be defined"); `endif @@ -125,6 +149,9 @@ module \$__mul (A, B, Y); .B(B), .Y(partial[i]) ); + // TODO: Currently a 'cascade' approach to summing the partial + // products is taken here, but a more efficient 'binary + // reduction' approach also exists... assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; end @@ -182,6 +209,9 @@ module \$__mul (A, B, Y); .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}), .Y(partial[i]) ); + // TODO: Currently a 'cascade' approach to summing the partial + // products is taken here, but a more efficient 'binary + // reduction' approach also exists... assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; end -- cgit v1.2.3 From 2f71c2c2198b05e216524feb94b66d14c9c433c0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 26 Jul 2019 15:30:51 -0700 Subject: Fix spacing --- techlibs/common/mul2dsp.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index a8c2dcccc..678de3796 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -149,9 +149,9 @@ module \$__mul (A, B, Y); .B(B), .Y(partial[i]) ); - // TODO: Currently a 'cascade' approach to summing the partial - // products is taken here, but a more efficient 'binary - // reduction' approach also exists... + // TODO: Currently a 'cascade' approach to summing the partial + // products is taken here, but a more efficient 'binary + // reduction' approach also exists... assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; end -- cgit v1.2.3 From 60c4887d15f89499d351fe9bd9ed36a5a4c1fe37 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 31 Jul 2019 15:45:41 -0700 Subject: For signed multipliers, compute sign bit separately... --- techlibs/common/mul2dsp.v | 65 ++++++++++++++++++++++++++++++----------------- 1 file changed, 42 insertions(+), 23 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 678de3796..b745547a8 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -54,8 +54,22 @@ module \$mul (A, B, Y); generate if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1) wire _TECHMAP_FAIL_ = 1; - // NB: A_SIGNED == B_SIGNED == 0 from here - else if (A_WIDTH >= B_WIDTH) + // NB: A_SIGNED == B_SIGNED from here + else if (A_WIDTH < B_WIDTH) + \$mul #( + .A_SIGNED(B_SIGNED), + .B_SIGNED(A_SIGNED), + .A_WIDTH(B_WIDTH), + .B_WIDTH(A_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A(B), + .B(A), + .Y(Y) + ); + else if (A_SIGNED && (A_WIDTH > `DSP_A_MAXWIDTH || B_WIDTH > `DSP_B_MAXWIDTH)) begin + wire _; + assign Y[Y_WIDTH-1] = A[A_WIDTH-1] ^ B[B_WIDTH-1]; \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), @@ -65,18 +79,19 @@ module \$mul (A, B, Y); ) _TECHMAP_REPLACE_ ( .A(A), .B(B), - .Y(Y) + .Y({_,Y[Y_WIDTH-2:0]}) ); + end else \$__mul #( - .A_SIGNED(B_SIGNED), - .B_SIGNED(A_SIGNED), - .A_WIDTH(B_WIDTH), - .B_WIDTH(A_WIDTH), + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH) ) _TECHMAP_REPLACE_ ( - .A(B), - .B(A), + .A(A), + .B(B), .Y(Y) ); endgenerate @@ -209,23 +224,27 @@ module \$__mul (A, B, Y); .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}), .Y(partial[i]) ); - // TODO: Currently a 'cascade' approach to summing the partial - // products is taken here, but a more efficient 'binary - // reduction' approach also exists... + // TODO: Currently a 'cascade' approach to summing the partial + // products is taken here, but a more efficient 'binary + // reduction' approach also exists... assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; end - \$__mul #( - .A_SIGNED(A_SIGNED), - .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom)), - .Y_WIDTH(last_Y_WIDTH) - ) mul_last ( - .A(A), - .B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]), - .Y(last_partial) - ); + localparam last_B_WIDTH = B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom); + if (A_SIGNED && B_SIGNED && last_B_WIDTH == 1) + assign last_partial = 0; + else + \$__mul #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(last_B_WIDTH), + .Y_WIDTH(last_Y_WIDTH) + ) mul_last ( + .A(A), + .B(B[B_WIDTH-1 -: last_B_WIDTH]), + .Y(last_partial) + ); assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; assign Y = partial_sum[n-1]; end -- cgit v1.2.3 From d2c33863d08bbc506888b723a304aa11f8650296 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 31 Jul 2019 16:04:19 -0700 Subject: Do not compute sign bit if result is zero --- techlibs/common/mul2dsp.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index b745547a8..bfd216fbf 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -69,7 +69,6 @@ module \$mul (A, B, Y); ); else if (A_SIGNED && (A_WIDTH > `DSP_A_MAXWIDTH || B_WIDTH > `DSP_B_MAXWIDTH)) begin wire _; - assign Y[Y_WIDTH-1] = A[A_WIDTH-1] ^ B[B_WIDTH-1]; \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), @@ -81,6 +80,8 @@ module \$mul (A, B, Y); .B(B), .Y({_,Y[Y_WIDTH-2:0]}) ); + // For non-zero results, recompute sign bit + assign Y[Y_WIDTH-1] = (|Y[Y_WIDTH-2:0]) & (A[A_WIDTH-1] ^ B[B_WIDTH-1]); end else \$__mul #( -- cgit v1.2.3 From 7e86c8bcfb10f6a819273ad8bd10fa461987f2f1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 1 Aug 2019 10:01:43 -0700 Subject: Fix B_WIDTH > DSP_B_MAXWIDTH case --- techlibs/common/mul2dsp.v | 46 ++++++++++++++-------------------------------- 1 file changed, 14 insertions(+), 32 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index bfd216fbf..b28a4247e 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -67,22 +67,6 @@ module \$mul (A, B, Y); .B(A), .Y(Y) ); - else if (A_SIGNED && (A_WIDTH > `DSP_A_MAXWIDTH || B_WIDTH > `DSP_B_MAXWIDTH)) begin - wire _; - \$__mul #( - .A_SIGNED(A_SIGNED), - .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH), - .Y_WIDTH(Y_WIDTH) - ) _TECHMAP_REPLACE_ ( - .A(A), - .B(B), - .Y({_,Y[Y_WIDTH-2:0]}) - ); - // For non-zero results, recompute sign bit - assign Y[Y_WIDTH-1] = (|Y[Y_WIDTH-2:0]) & (A[A_WIDTH-1] ^ B[B_WIDTH-1]); - end else \$__mul #( .A_SIGNED(A_SIGNED), @@ -171,14 +155,15 @@ module \$__mul (A, B, Y); assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; end + localparam last_A_WIDTH = A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom); \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)), + .A_WIDTH(last_A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(last_Y_WIDTH) ) mul_slice_last ( - .A(A[A_WIDTH-1 : (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]), + .A(A[A_WIDTH-1 -: last_A_WIDTH]), .B(B), .Y(last_partial) ); @@ -232,20 +217,17 @@ module \$__mul (A, B, Y); end localparam last_B_WIDTH = B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom); - if (A_SIGNED && B_SIGNED && last_B_WIDTH == 1) - assign last_partial = 0; - else - \$__mul #( - .A_SIGNED(A_SIGNED), - .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH), - .B_WIDTH(last_B_WIDTH), - .Y_WIDTH(last_Y_WIDTH) - ) mul_last ( - .A(A), - .B(B[B_WIDTH-1 -: last_B_WIDTH]), - .Y(last_partial) - ); + \$__mul #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(last_B_WIDTH), + .Y_WIDTH(last_Y_WIDTH) + ) mul_last ( + .A(A), + .B(B[B_WIDTH-1 -: last_B_WIDTH]), + .Y(last_partial) + ); assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; assign Y = partial_sum[n-1]; end -- cgit v1.2.3 From 332b86491de4d033f2fe259ab7ad7d02761cc515 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 1 Aug 2019 12:17:14 -0700 Subject: Revert "Do not do sign extension in techmap; let packer do it" This reverts commit 595a8f032f1e9db385959f92a4a414a40de291fd. --- techlibs/common/mul2dsp.v | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index b28a4247e..99afce18c 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -232,15 +232,24 @@ module \$__mul (A, B, Y); assign Y = partial_sum[n-1]; end else begin + if (A_SIGNED) + wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A); + else + wire [`DSP_A_MAXWIDTH-1:0] Aext = A; + if (B_SIGNED) + wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B); + else + wire [`DSP_B_MAXWIDTH-1:0] Bext = B; + `DSP_NAME #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH), - .Y_WIDTH(`MIN(Y_WIDTH,A_WIDTH+B_WIDTH)), + .A_WIDTH(`DSP_A_MAXWIDTH), + .B_WIDTH(`DSP_B_MAXWIDTH), + .Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)), ) _TECHMAP_REPLACE_ ( - .A(A), - .B(B), + .A(Aext), + .B(Bext), .Y(Y) ); end -- cgit v1.2.3 From 915f4e34bfdf1fd2b9f97d1c15a55e2c4c49f428 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 1 Aug 2019 13:20:34 -0700 Subject: DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH --- techlibs/common/mul2dsp.v | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 99afce18c..5ff0e03aa 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -52,7 +52,7 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1) + if (A_SIGNED != B_SIGNED) wire _TECHMAP_FAIL_ = 1; // NB: A_SIGNED == B_SIGNED from here else if (A_WIDTH < B_WIDTH) @@ -103,10 +103,17 @@ module \$__mul (A, B, Y); genvar i; generate - if (A_WIDTH <= 1 || B_WIDTH <= 1) + if (0) begin end +`ifdef DSP_A_MINWIDTH + else if (A_WIDTH < `DSP_A_MINWIDTH) wire _TECHMAP_FAIL_ = 1; -`ifdef DSP_MINWIDTH - else if (A_WIDTH+B_WIDTH < `DSP_MINWIDTH || Y_WIDTH < `DSP_MINWIDTH) +`endif +`ifdef DSP_B_MINWIDTH + else if (B_WIDTH < `DSP_B_MINWIDTH) + wire _TECHMAP_FAIL_ = 1; +`endif +`ifdef DSP_Y_MINWIDTH + else if (Y_WIDTH < `DSP_Y_MINWIDTH) wire _TECHMAP_FAIL_ = 1; `endif else if (A_WIDTH > `DSP_A_MAXWIDTH) begin -- cgit v1.2.3 From 65de9aaaa9d744686e235ff8701cd997cd2dc891 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 1 Aug 2019 14:29:00 -0700 Subject: Add DSP_SIGNEDONLY back --- techlibs/common/mul2dsp.v | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 5ff0e03aa..6cd5128a6 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -55,6 +55,22 @@ module \$mul (A, B, Y); if (A_SIGNED != B_SIGNED) wire _TECHMAP_FAIL_ = 1; // NB: A_SIGNED == B_SIGNED from here +`ifdef DSP_SIGNEDONLY + else if (!A_SIGNED) begin + wire [1:0] _; + \$mul #( + .A_SIGNED(1), + .B_SIGNED(1), + .A_WIDTH(A_WIDTH + 1), + .B_WIDTH(B_WIDTH + 1), + .Y_WIDTH(Y_WIDTH + 2) + ) _TECHMAP_REPLACE_ ( + .A({1'b0, A}), + .B({1'b0, B}), + .Y({_, Y}) + ); + end +`endif else if (A_WIDTH < B_WIDTH) \$mul #( .A_SIGNED(B_SIGNED), -- cgit v1.2.3 From 105aaeaf598a04020fa5030c947f623f0daa38da Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 1 Aug 2019 14:33:16 -0700 Subject: Trim Y_WIDTH --- techlibs/common/mul2dsp.v | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 6cd5128a6..8e37201e2 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -56,20 +56,18 @@ module \$mul (A, B, Y); wire _TECHMAP_FAIL_ = 1; // NB: A_SIGNED == B_SIGNED from here `ifdef DSP_SIGNEDONLY - else if (!A_SIGNED) begin - wire [1:0] _; + else if (!A_SIGNED) \$mul #( .A_SIGNED(1), .B_SIGNED(1), .A_WIDTH(A_WIDTH + 1), .B_WIDTH(B_WIDTH + 1), - .Y_WIDTH(Y_WIDTH + 2) + .Y_WIDTH(Y_WIDTH) ) _TECHMAP_REPLACE_ ( .A({1'b0, A}), .B({1'b0, B}), - .Y({_, Y}) + .Y(Y) ); - end `endif else if (A_WIDTH < B_WIDTH) \$mul #( -- cgit v1.2.3 From 2a1b98d478918b0a17c7e509ada6e7a71bbab526 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 13 Aug 2019 10:21:24 -0700 Subject: Add DSP_A_MAXWIDTH_PARTIAL, refactor --- techlibs/common/mul2dsp.v | 254 ++++++++++++++++++++-------------------------- 1 file changed, 110 insertions(+), 144 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 8e37201e2..71d5a5454 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -27,20 +27,30 @@ */ `ifndef DSP_A_MAXWIDTH -$error("Macro DSP_A_MAXWIDTH must be defined"); +$fatal(1, "Macro DSP_A_MAXWIDTH must be defined"); `endif `ifndef DSP_B_MAXWIDTH -$error("Macro DSP_B_MAXWIDTH must be defined"); +$fatal(1, "Macro DSP_B_MAXWIDTH must be defined"); +`endif +`ifndef DSP_B_MAXWIDTH +$fatal(1, "Macro DSP_B_MAXWIDTH must be defined"); +`endif +`ifndef DSP_A_MAXWIDTH_PARTIAL +`define DSP_A_MAXWIDTH_PARTIAL `DSP_A_MAXWIDTH +`endif +`ifndef DSP_B_MAXWIDTH_PARTIAL +`define DSP_B_MAXWIDTH_PARTIAL `DSP_B_MAXWIDTH `endif `ifndef DSP_NAME -$error("Macro DSP_NAME must be defined"); +$fatal(1, "Macro DSP_NAME must be defined"); `endif `define MAX(a,b) (a > b ? a : b) `define MIN(a,b) (a < b ? a : b) -module \$mul (A, B, Y); +(* techmap_celltype = "$mul $__mul" *) +module _80_mul (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 1; @@ -51,12 +61,26 @@ module \$mul (A, B, Y); input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; + parameter _TECHMAP_CELLTYPE_ = ""; + generate - if (A_SIGNED != B_SIGNED) + if (0) begin end +`ifdef DSP_A_MINWIDTH + else if (A_WIDTH < `DSP_A_MINWIDTH) + wire _TECHMAP_FAIL_ = 1; +`endif +`ifdef DSP_B_MINWIDTH + else if (B_WIDTH < `DSP_B_MINWIDTH) + wire _TECHMAP_FAIL_ = 1; +`endif +`ifdef DSP_Y_MINWIDTH + else if (Y_WIDTH < `DSP_Y_MINWIDTH) + wire _TECHMAP_FAIL_ = 1; +`endif + else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED) wire _TECHMAP_FAIL_ = 1; - // NB: A_SIGNED == B_SIGNED from here `ifdef DSP_SIGNEDONLY - else if (!A_SIGNED) + else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED) \$mul #( .A_SIGNED(1), .B_SIGNED(1), @@ -81,102 +105,53 @@ module \$mul (A, B, Y); .B(A), .Y(Y) ); - else - \$__mul #( - .A_SIGNED(A_SIGNED), - .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH), - .Y_WIDTH(Y_WIDTH) - ) _TECHMAP_REPLACE_ ( - .A(A), - .B(B), - .Y(Y) - ); - endgenerate -endmodule - -module \$__mul (A, B, Y); - parameter A_SIGNED = 0; - parameter B_SIGNED = 0; - parameter A_WIDTH = 1; - parameter B_WIDTH = 1; - parameter Y_WIDTH = 1; - - input [A_WIDTH-1:0] A; - input [B_WIDTH-1:0] B; - output [Y_WIDTH-1:0] Y; - - wire [1023:0] _TECHMAP_DO_ = "proc; clean"; + else begin + wire [1023:0] _TECHMAP_DO_ = "proc; clean"; `ifdef DSP_SIGNEDONLY - localparam sign_headroom = 1; + localparam sign_headroom = 1; `else - localparam sign_headroom = 0; + localparam sign_headroom = 0; `endif - genvar i; - generate - if (0) begin end -`ifdef DSP_A_MINWIDTH - else if (A_WIDTH < `DSP_A_MINWIDTH) - wire _TECHMAP_FAIL_ = 1; -`endif -`ifdef DSP_B_MINWIDTH - else if (B_WIDTH < `DSP_B_MINWIDTH) - wire _TECHMAP_FAIL_ = 1; -`endif -`ifdef DSP_Y_MINWIDTH - else if (Y_WIDTH < `DSP_Y_MINWIDTH) - wire _TECHMAP_FAIL_ = 1; -`endif - else if (A_WIDTH > `DSP_A_MAXWIDTH) begin - localparam n = (A_WIDTH+`DSP_A_MAXWIDTH-sign_headroom-1) / (`DSP_A_MAXWIDTH-sign_headroom); - localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); - localparam last_Y_WIDTH = `MIN(partial_Y_WIDTH, B_WIDTH+A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)); + genvar i; + if (A_WIDTH > `DSP_A_MAXWIDTH) begin + localparam n = (A_WIDTH-`DSP_A_MAXWIDTH+`DSP_A_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_A_MAXWIDTH_PARTIAL-sign_headroom); + localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL); + localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom); + localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH; if (A_SIGNED && B_SIGNED) begin - wire signed [partial_Y_WIDTH-1:0] partial [n-2:0]; + wire signed [partial_Y_WIDTH-1:0] partial [n-1:0]; wire signed [last_Y_WIDTH-1:0] last_partial; - wire signed [Y_WIDTH-1:0] partial_sum [n-1:0]; + wire signed [Y_WIDTH-1:0] partial_sum [n:0]; end else begin wire [partial_Y_WIDTH-1:0] partial [n-1:0]; wire [last_Y_WIDTH-1:0] last_partial; - wire [Y_WIDTH-1:0] partial_sum [n-1:0]; + wire [Y_WIDTH-1:0] partial_sum [n:0]; end - \$__mul #( - .A_SIGNED(sign_headroom), - .B_SIGNED(B_SIGNED), - .A_WIDTH(`DSP_A_MAXWIDTH), - .B_WIDTH(B_WIDTH), - .Y_WIDTH(partial_Y_WIDTH) - ) mul_slice_first ( - .A({{sign_headroom{1'b0}}, A[`DSP_A_MAXWIDTH-sign_headroom-1 : 0]}), - .B(B), - .Y(partial[0]) - ); - assign partial_sum[0] = partial[0]; - - for (i = 1; i < n-1; i=i+1) begin:slice + for (i = 0; i < n; i=i+1) begin:slice \$__mul #( .A_SIGNED(sign_headroom), .B_SIGNED(B_SIGNED), - .A_WIDTH(`DSP_A_MAXWIDTH), + .A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL), .B_WIDTH(B_WIDTH), .Y_WIDTH(partial_Y_WIDTH) ) mul_slice ( - .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH-sign_headroom) +: `DSP_A_MAXWIDTH-sign_headroom]}), + .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}), .B(B), .Y(partial[i]) ); // TODO: Currently a 'cascade' approach to summing the partial // products is taken here, but a more efficient 'binary // reduction' approach also exists... - assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; + if (i == 0) + assign partial_sum[i] = partial[i]; + else + assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; end - localparam last_A_WIDTH = A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom); \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), @@ -188,56 +163,46 @@ module \$__mul (A, B, Y); .B(B), .Y(last_partial) ); - assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; - assign Y = partial_sum[n-1]; + assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; + assign Y = partial_sum[n]; end else if (B_WIDTH > `DSP_B_MAXWIDTH) begin - localparam n = (B_WIDTH+`DSP_B_MAXWIDTH-sign_headroom-1) / (`DSP_B_MAXWIDTH-sign_headroom); - localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH); - localparam last_Y_WIDTH = `MIN(partial_Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom)); + localparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom); + localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL); + localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom); + localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH; if (A_SIGNED && B_SIGNED) begin - wire signed [partial_Y_WIDTH-1:0] partial [n-2:0]; + wire signed [partial_Y_WIDTH-1:0] partial [n-1:0]; wire signed [last_Y_WIDTH-1:0] last_partial; - wire signed [Y_WIDTH-1:0] partial_sum [n-1:0]; + wire signed [Y_WIDTH-1:0] partial_sum [n:0]; end else begin wire [partial_Y_WIDTH-1:0] partial [n-1:0]; wire [last_Y_WIDTH-1:0] last_partial; - wire [Y_WIDTH-1:0] partial_sum [n-1:0]; + wire [Y_WIDTH-1:0] partial_sum [n:0]; end - \$__mul #( - .A_SIGNED(A_SIGNED), - .B_SIGNED(sign_headroom), - .A_WIDTH(A_WIDTH), - .B_WIDTH(`DSP_B_MAXWIDTH), - .Y_WIDTH(partial_Y_WIDTH) - ) mul_first ( - .A(A), - .B({{sign_headroom{1'b0}}, B[`DSP_B_MAXWIDTH-sign_headroom-1 : 0]}), - .Y(partial[0]) - ); - assign partial_sum[0] = partial[0]; - - for (i = 1; i < n-1; i=i+1) begin:slice + for (i = 0; i < n; i=i+1) begin:slice \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(sign_headroom), .A_WIDTH(A_WIDTH), - .B_WIDTH(`DSP_B_MAXWIDTH), + .B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL), .Y_WIDTH(partial_Y_WIDTH) ) mul ( .A(A), - .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}), + .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}), .Y(partial[i]) ); - // TODO: Currently a 'cascade' approach to summing the partial + // TODO: Currently a 'cascade' approach to summing the partial // products is taken here, but a more efficient 'binary // reduction' approach also exists... - assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; + if (i == 0) + assign partial_sum[i] = partial[i]; + else + assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; end - localparam last_B_WIDTH = B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom); \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), @@ -249,10 +214,10 @@ module \$__mul (A, B, Y); .B(B[B_WIDTH-1 -: last_B_WIDTH]), .Y(last_partial) ); - assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; - assign Y = partial_sum[n-1]; + assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; + assign Y = partial_sum[n]; end - else begin + else begin if (A_SIGNED) wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A); else @@ -274,11 +239,12 @@ module \$__mul (A, B, Y); .Y(Y) ); end + end endgenerate endmodule -(* techmap_celltype = "$__mul" *) -module $__soft_mul (A, B, Y); +(* techmap_celltype = "$mul $__mul" *) +module _90_soft_mul (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 1; @@ -292,41 +258,41 @@ module $__soft_mul (A, B, Y); // Indirection necessary since mapping // back to $mul will cause recursion generate - if (A_SIGNED && !B_SIGNED) - \$__soft__mul #( - .A_SIGNED(A_SIGNED), - .B_SIGNED(1), - .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH+1), - .Y_WIDTH(Y_WIDTH) - ) _TECHMAP_REPLACE_ ( - .A(A), - .B({1'b0,B}), - .Y(Y) - ); - else if (!A_SIGNED && B_SIGNED) - \$__soft_mul #( - .A_SIGNED(1), - .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH+1), - .B_WIDTH(B_WIDTH), - .Y_WIDTH(Y_WIDTH) - ) _TECHMAP_REPLACE_ ( - .A({1'b0,A}), - .B(B), - .Y(Y) - ); - else - \$__soft_mul #( - .A_SIGNED(A_SIGNED), - .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH), - .Y_WIDTH(Y_WIDTH) - ) _TECHMAP_REPLACE_ ( - .A(A), - .B(B), - .Y(Y) - ); + if (A_SIGNED && !B_SIGNED) + \$__soft_mul #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(1), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH+1), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A(A), + .B({1'b0,B}), + .Y(Y) + ); + else if (!A_SIGNED && B_SIGNED) + \$__soft_mul #( + .A_SIGNED(1), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH+1), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A({1'b0,A}), + .B(B), + .Y(Y) + ); + else + \$__soft_mul #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A(A), + .B(B), + .Y(Y) + ); endgenerate endmodule -- cgit v1.2.3 From e35dfc5ab591968d86259b90a643f1545e79e661 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 13 Aug 2019 16:52:15 -0700 Subject: Only swap ports if $mul and not $__mul --- techlibs/common/mul2dsp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 71d5a5454..75b1242a2 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -93,7 +93,7 @@ module _80_mul (A, B, Y); .Y(Y) ); `endif - else if (A_WIDTH < B_WIDTH) + else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH) \$mul #( .A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), -- cgit v1.2.3 From 76eedee08928f035f00f46304d1b49e9502401c1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 10 Sep 2019 14:26:12 -0700 Subject: Really get rid of 'opt_expr -fine' by being explicit --- techlibs/common/mul2dsp.v | 39 +++++++++++++++++++++++++++++++++------ 1 file changed, 33 insertions(+), 6 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 75b1242a2..51a6c5fb9 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -148,8 +148,17 @@ module _80_mul (A, B, Y); // reduction' approach also exists... if (i == 0) assign partial_sum[i] = partial[i]; - else - assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; + else begin + // Rewrite the following statement explicitly in order + // to save on a call to 'opt_expr -fine' which would + // optimise away the '<<' op and trim size of adder + //assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; + wire [Y_WIDTH-1:0] shifted_sum = {partial[i], {i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}}; + assign partial_sum[i] = { + partial_sum[i-1][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0], + shifted_sum[Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] + }; + end end \$__mul #( @@ -163,7 +172,12 @@ module _80_mul (A, B, Y); .B(B), .Y(last_partial) ); - assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; + //assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; + wire [Y_WIDTH-1:0] shifted_sum = {last_partial, {n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}}; + assign partial_sum[n] = { + partial_sum[n-1][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0], + shifted_sum[Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] + }; assign Y = partial_sum[n]; end else if (B_WIDTH > `DSP_B_MAXWIDTH) begin @@ -199,8 +213,16 @@ module _80_mul (A, B, Y); // reduction' approach also exists... if (i == 0) assign partial_sum[i] = partial[i]; - else - assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; + else begin + // Rewrite the following statement explicitly in order + // to save on a call to 'opt_expr -fine' which would + // optimise away the '<<' op and trim size of adder + wire [Y_WIDTH-1:0] shifted_sum = {partial[i], {i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}}; + assign partial_sum[i] = { + partial_sum[i-1][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0], + shifted_sum[Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] + }; + end end \$__mul #( @@ -214,7 +236,12 @@ module _80_mul (A, B, Y); .B(B[B_WIDTH-1 -: last_B_WIDTH]), .Y(last_partial) ); - assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; + //assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; + wire [Y_WIDTH-1:0] shifted_sum = {last_partial, {n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}}; + assign partial_sum[n] = { + partial_sum[n-1][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0], + shifted_sum[Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] + }; assign Y = partial_sum[n]; end else begin -- cgit v1.2.3 From f2d030a70f1754e7ee6bd1fb588c5abadac4dd08 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 10 Sep 2019 15:14:55 -0700 Subject: Be sensitive to signedness --- techlibs/common/mul2dsp.v | 41 +++++++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 20 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 51a6c5fb9..f2b44222e 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -153,11 +153,11 @@ module _80_mul (A, B, Y); // to save on a call to 'opt_expr -fine' which would // optimise away the '<<' op and trim size of adder //assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; - wire [Y_WIDTH-1:0] shifted_sum = {partial[i], {i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}}; - assign partial_sum[i] = { - partial_sum[i-1][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0], - shifted_sum[Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] - }; + if (A_SIGNED && B_SIGNED) + assign partial_sum[i][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + $signed(partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]); + else + assign partial_sum[i][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]; + assign partial_sum[i][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[i-1][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0]; end end @@ -173,11 +173,11 @@ module _80_mul (A, B, Y); .Y(last_partial) ); //assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; - wire [Y_WIDTH-1:0] shifted_sum = {last_partial, {n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}}; - assign partial_sum[n] = { - partial_sum[n-1][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0], - shifted_sum[Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] - }; + if (A_SIGNED && B_SIGNED) + assign partial_sum[n][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + $signed(partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]); + else + assign partial_sum[n][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]; + assign partial_sum[n][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[n-1][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0]; assign Y = partial_sum[n]; end else if (B_WIDTH > `DSP_B_MAXWIDTH) begin @@ -217,11 +217,12 @@ module _80_mul (A, B, Y); // Rewrite the following statement explicitly in order // to save on a call to 'opt_expr -fine' which would // optimise away the '<<' op and trim size of adder - wire [Y_WIDTH-1:0] shifted_sum = {partial[i], {i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}}; - assign partial_sum[i] = { - partial_sum[i-1][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0], - shifted_sum[Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] - }; + //assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; + if (A_SIGNED && B_SIGNED) + assign partial_sum[i][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + $signed(partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]); + else + assign partial_sum[i][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]; + assign partial_sum[i][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[i-1][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0]; end end @@ -237,11 +238,11 @@ module _80_mul (A, B, Y); .Y(last_partial) ); //assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; - wire [Y_WIDTH-1:0] shifted_sum = {last_partial, {n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}}; - assign partial_sum[n] = { - partial_sum[n-1][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0], - shifted_sum[Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] - }; + if (A_SIGNED && B_SIGNED) + assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]; + else + assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + $signed(partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]); + assign partial_sum[n][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[n-1][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0]; assign Y = partial_sum[n]; end else begin -- cgit v1.2.3 From ab46d9017b1a6fe6e376278ca9d3bec2e5673f06 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 20 Sep 2019 10:11:36 -0700 Subject: Fix signedness bug --- techlibs/common/mul2dsp.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index f2b44222e..3ca69b7b1 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -239,9 +239,9 @@ module _80_mul (A, B, Y); ); //assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; if (A_SIGNED && B_SIGNED) - assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]; - else assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + $signed(partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]); + else + assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]; assign partial_sum[n][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[n-1][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0]; assign Y = partial_sum[n]; end -- cgit v1.2.3 From 1d875ac76a354f654f28b9632d83f6b43542e827 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 25 Sep 2019 14:06:21 -0700 Subject: No need for $__mul anymore? --- techlibs/common/mul2dsp.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 3ca69b7b1..25ff28ab5 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -49,7 +49,7 @@ $fatal(1, "Macro DSP_NAME must be defined"); `define MAX(a,b) (a > b ? a : b) `define MIN(a,b) (a < b ? a : b) -(* techmap_celltype = "$mul $__mul" *) +(* techmap_celltype = "$mul" *) module _80_mul (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; @@ -132,9 +132,9 @@ module _80_mul (A, B, Y); end for (i = 0; i < n; i=i+1) begin:slice - \$__mul #( + \$mul #( .A_SIGNED(sign_headroom), - .B_SIGNED(B_SIGNED), + .B_SIGNED(sign_headroom), .A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL), .B_WIDTH(B_WIDTH), .Y_WIDTH(partial_Y_WIDTH) @@ -161,7 +161,7 @@ module _80_mul (A, B, Y); end end - \$__mul #( + \$mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(last_A_WIDTH), @@ -197,8 +197,8 @@ module _80_mul (A, B, Y); end for (i = 0; i < n; i=i+1) begin:slice - \$__mul #( - .A_SIGNED(A_SIGNED), + \$mul #( + .A_SIGNED(sign_headroom), .B_SIGNED(sign_headroom), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL), @@ -226,7 +226,7 @@ module _80_mul (A, B, Y); end end - \$__mul #( + \$mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), @@ -271,7 +271,7 @@ module _80_mul (A, B, Y); endgenerate endmodule -(* techmap_celltype = "$mul $__mul" *) +(* techmap_celltype = "$mul" *) module _90_soft_mul (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; -- cgit v1.2.3 From 234738b103d4f2b3d937ed928fd89bc4e31627f1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 25 Sep 2019 16:51:31 -0700 Subject: Remove _TECHMAP_CELLTYPE_ check since all $mul --- techlibs/common/mul2dsp.v | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 25ff28ab5..8c6a836f8 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -61,8 +61,6 @@ module _80_mul (A, B, Y); input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; - parameter _TECHMAP_CELLTYPE_ = ""; - generate if (0) begin end `ifdef DSP_A_MINWIDTH @@ -77,10 +75,8 @@ module _80_mul (A, B, Y); else if (Y_WIDTH < `DSP_Y_MINWIDTH) wire _TECHMAP_FAIL_ = 1; `endif - else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED) - wire _TECHMAP_FAIL_ = 1; `ifdef DSP_SIGNEDONLY - else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED) + else if (!A_SIGNED) \$mul #( .A_SIGNED(1), .B_SIGNED(1), @@ -93,7 +89,7 @@ module _80_mul (A, B, Y); .Y(Y) ); `endif - else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH) + else if (A_WIDTH < B_WIDTH) \$mul #( .A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), -- cgit v1.2.3 From f4387e817c3f75a06c9c94f307fa60572ea06383 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 25 Sep 2019 17:24:11 -0700 Subject: Revert "No need for $__mul anymore?" This reverts commit 1d875ac76a354f654f28b9632d83f6b43542e827. --- techlibs/common/mul2dsp.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 8c6a836f8..953fc28d1 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -49,7 +49,7 @@ $fatal(1, "Macro DSP_NAME must be defined"); `define MAX(a,b) (a > b ? a : b) `define MIN(a,b) (a < b ? a : b) -(* techmap_celltype = "$mul" *) +(* techmap_celltype = "$mul $__mul" *) module _80_mul (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; @@ -128,9 +128,9 @@ module _80_mul (A, B, Y); end for (i = 0; i < n; i=i+1) begin:slice - \$mul #( + \$__mul #( .A_SIGNED(sign_headroom), - .B_SIGNED(sign_headroom), + .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL), .B_WIDTH(B_WIDTH), .Y_WIDTH(partial_Y_WIDTH) @@ -157,7 +157,7 @@ module _80_mul (A, B, Y); end end - \$mul #( + \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(last_A_WIDTH), @@ -193,8 +193,8 @@ module _80_mul (A, B, Y); end for (i = 0; i < n; i=i+1) begin:slice - \$mul #( - .A_SIGNED(sign_headroom), + \$__mul #( + .A_SIGNED(A_SIGNED), .B_SIGNED(sign_headroom), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL), @@ -222,7 +222,7 @@ module _80_mul (A, B, Y); end end - \$mul #( + \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), @@ -267,7 +267,7 @@ module _80_mul (A, B, Y); endgenerate endmodule -(* techmap_celltype = "$mul" *) +(* techmap_celltype = "$mul $__mul" *) module _90_soft_mul (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; -- cgit v1.2.3 From a4238637acc4e6670ccefb1894b00c602a827408 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 25 Sep 2019 17:25:44 -0700 Subject: Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" This reverts commit 234738b103d4f2b3d937ed928fd89bc4e31627f1. --- techlibs/common/mul2dsp.v | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 953fc28d1..3ca69b7b1 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -61,6 +61,8 @@ module _80_mul (A, B, Y); input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; + parameter _TECHMAP_CELLTYPE_ = ""; + generate if (0) begin end `ifdef DSP_A_MINWIDTH @@ -75,8 +77,10 @@ module _80_mul (A, B, Y); else if (Y_WIDTH < `DSP_Y_MINWIDTH) wire _TECHMAP_FAIL_ = 1; `endif + else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED) + wire _TECHMAP_FAIL_ = 1; `ifdef DSP_SIGNEDONLY - else if (!A_SIGNED) + else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED) \$mul #( .A_SIGNED(1), .B_SIGNED(1), @@ -89,7 +93,7 @@ module _80_mul (A, B, Y); .Y(Y) ); `endif - else if (A_WIDTH < B_WIDTH) + else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH) \$mul #( .A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), -- cgit v1.2.3 From 34aa3532fb1df2300da83df4071b46da69e3723c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 25 Sep 2019 17:26:47 -0700 Subject: Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit --- techlibs/common/mul2dsp.v | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 3ca69b7b1..9932e288f 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -77,10 +77,8 @@ module _80_mul (A, B, Y); else if (Y_WIDTH < `DSP_Y_MINWIDTH) wire _TECHMAP_FAIL_ = 1; `endif - else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED) - wire _TECHMAP_FAIL_ = 1; `ifdef DSP_SIGNEDONLY - else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED) + else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED && !B_SIGNED) \$mul #( .A_SIGNED(1), .B_SIGNED(1), -- cgit v1.2.3 From 35aaa8d73a75f36a42eea9ef2b210d9e79e5edc3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 25 Sep 2019 22:58:55 -0700 Subject: mul2dsp.v slice names --- techlibs/common/mul2dsp.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 9932e288f..60b180ac0 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -129,14 +129,14 @@ module _80_mul (A, B, Y); wire [Y_WIDTH-1:0] partial_sum [n:0]; end - for (i = 0; i < n; i=i+1) begin:slice + for (i = 0; i < n; i=i+1) begin:sliceA \$__mul #( .A_SIGNED(sign_headroom), .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL), .B_WIDTH(B_WIDTH), .Y_WIDTH(partial_Y_WIDTH) - ) mul_slice ( + ) mul ( .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}), .B(B), .Y(partial[i]) @@ -165,7 +165,7 @@ module _80_mul (A, B, Y); .A_WIDTH(last_A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(last_Y_WIDTH) - ) mul_slice_last ( + ) sliceA.last ( .A(A[A_WIDTH-1 -: last_A_WIDTH]), .B(B), .Y(last_partial) @@ -194,7 +194,7 @@ module _80_mul (A, B, Y); wire [Y_WIDTH-1:0] partial_sum [n:0]; end - for (i = 0; i < n; i=i+1) begin:slice + for (i = 0; i < n; i=i+1) begin:sliceB \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(sign_headroom), @@ -230,7 +230,7 @@ module _80_mul (A, B, Y); .A_WIDTH(A_WIDTH), .B_WIDTH(last_B_WIDTH), .Y_WIDTH(last_Y_WIDTH) - ) mul_last ( + ) mul_sliceB_last ( .A(A), .B(B[B_WIDTH-1 -: last_B_WIDTH]), .Y(last_partial) -- cgit v1.2.3 From 27e5bf5aad229ef330bfea932f6b194ec5c09b68 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 26 Sep 2019 09:57:11 -0700 Subject: Stop trying to be too smart by prematurely optimising --- techlibs/common/mul2dsp.v | 40 ++++++---------------------------------- 1 file changed, 6 insertions(+), 34 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 60b180ac0..6dcdcf226 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -146,17 +146,8 @@ module _80_mul (A, B, Y); // reduction' approach also exists... if (i == 0) assign partial_sum[i] = partial[i]; - else begin - // Rewrite the following statement explicitly in order - // to save on a call to 'opt_expr -fine' which would - // optimise away the '<<' op and trim size of adder - //assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; - if (A_SIGNED && B_SIGNED) - assign partial_sum[i][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + $signed(partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]); - else - assign partial_sum[i][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]; - assign partial_sum[i][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[i-1][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0]; - end + else + assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1]; end \$__mul #( @@ -170,12 +161,7 @@ module _80_mul (A, B, Y); .B(B), .Y(last_partial) ); - //assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; - if (A_SIGNED && B_SIGNED) - assign partial_sum[n][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + $signed(partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]); - else - assign partial_sum[n][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]; - assign partial_sum[n][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[n-1][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0]; + assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1]; assign Y = partial_sum[n]; end else if (B_WIDTH > `DSP_B_MAXWIDTH) begin @@ -211,17 +197,8 @@ module _80_mul (A, B, Y); // reduction' approach also exists... if (i == 0) assign partial_sum[i] = partial[i]; - else begin - // Rewrite the following statement explicitly in order - // to save on a call to 'opt_expr -fine' which would - // optimise away the '<<' op and trim size of adder - //assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; - if (A_SIGNED && B_SIGNED) - assign partial_sum[i][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + $signed(partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]); - else - assign partial_sum[i][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]; - assign partial_sum[i][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[i-1][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0]; - end + else + assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; end \$__mul #( @@ -235,12 +212,7 @@ module _80_mul (A, B, Y); .B(B[B_WIDTH-1 -: last_B_WIDTH]), .Y(last_partial) ); - //assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; - if (A_SIGNED && B_SIGNED) - assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + $signed(partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]); - else - assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]; - assign partial_sum[n][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[n-1][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0]; + assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; assign Y = partial_sum[n]; end else begin -- cgit v1.2.3 From 90236025b7e1409027550451abe4ffc1cc63f128 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 27 Sep 2019 14:21:47 -0700 Subject: Missing (* mul2dsp *) for sliceB --- techlibs/common/mul2dsp.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/common/mul2dsp.v') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 6dcdcf226..4cabb4453 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -198,7 +198,7 @@ module _80_mul (A, B, Y); if (i == 0) assign partial_sum[i] = partial[i]; else - assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; + assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1]; end \$__mul #( @@ -212,7 +212,7 @@ module _80_mul (A, B, Y); .B(B[B_WIDTH-1 -: last_B_WIDTH]), .Y(last_partial) ); - assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; + assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1]; assign Y = partial_sum[n]; end else begin -- cgit v1.2.3