From b0bee396a8edec360616b68e97a3bd373b700b26 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Wed, 8 Apr 2020 21:42:50 +0200
Subject: Add new builtin FF types

The new types include:

- FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`)
- FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`)
- FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`)
- FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`)
- FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`)
- latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`)

The new FF types are not actually used anywhere yet (this is left
for future commits).
---
 techlibs/common/simcells.v | 2218 +++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 2101 insertions(+), 117 deletions(-)

(limited to 'techlibs/common/simcells.v')

diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 157e8d23b..01b5bdfa6 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -870,256 +870,2240 @@ endmodule
 
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
-//-     $_DFFSR_NNN_ (C, S, R, D, Q)
+//-     $_DFFE_NN0N_ (D, C, R, E, Q)
 //-
-//- A negative edge D-type flip-flop with negative polarity set and negative
-//- polarity reset.
+//- A negative edge D-type flip-flop with negative polarity reset and negative
+//- polarity clock enable.
 //-
-//- Truth table:    C S R D | Q
+//- Truth table:    D C R E | Q
 //-                ---------+---
 //-                 - - 0 - | 0
-//-                 - 0 - - | 1
-//-                 \ - - d | d
+//-                 d \ - 0 | d
 //-                 - - - - | q
 //-
-module \$_DFFSR_NNN_ (C, S, R, D, Q);
-input C, S, R, D;
+module \$_DFFE_NN0N_ (D, C, R, E, Q);
+input D, C, R, E;
 output reg Q;
-always @(negedge C, negedge S, negedge R) begin
+always @(negedge C or negedge R) begin
 	if (R == 0)
 		Q <= 0;
-	else if (S == 0)
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_NN0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity reset and positive
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 0 - | 0
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_NN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_NN1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set and negative
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 0 - | 1
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_NN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or negedge R) begin
+	if (R == 0)
 		Q <= 1;
-	else
+	else if (E == 0)
 		Q <= D;
 end
 endmodule
 
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
-//-     $_DFFSR_NNP_ (C, S, R, D, Q)
+//-     $_DFFE_NN1P_ (D, C, R, E, Q)
 //-
 //- A negative edge D-type flip-flop with negative polarity set and positive
-//- polarity reset.
+//- polarity clock enable.
 //-
-//- Truth table:    C S R D | Q
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 0 - | 1
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_NN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or negedge R) begin
+	if (R == 0)
+		Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_NP0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity reset and negative
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
 //-                ---------+---
 //-                 - - 1 - | 0
-//-                 - 0 - - | 1
-//-                 \ - - d | d
+//-                 d \ - 0 | d
 //-                 - - - - | q
 //-
-module \$_DFFSR_NNP_ (C, S, R, D, Q);
-input C, S, R, D;
+module \$_DFFE_NP0N_ (D, C, R, E, Q);
+input D, C, R, E;
 output reg Q;
-always @(negedge C, negedge S, posedge R) begin
+always @(negedge C or posedge R) begin
 	if (R == 1)
 		Q <= 0;
-	else if (S == 0)
-		Q <= 1;
-	else
+	else if (E == 0)
 		Q <= D;
 end
 endmodule
 
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
-//-     $_DFFSR_NPN_ (C, S, R, D, Q)
+//-     $_DFFE_NP0P_ (D, C, R, E, Q)
 //-
-//- A negative edge D-type flip-flop with positive polarity set and negative
-//- polarity reset.
+//- A negative edge D-type flip-flop with positive polarity reset and positive
+//- polarity clock enable.
 //-
-//- Truth table:    C S R D | Q
+//- Truth table:    D C R E | Q
 //-                ---------+---
-//-                 - - 0 - | 0
-//-                 - 1 - - | 1
-//-                 \ - - d | d
+//-                 - - 1 - | 0
+//-                 d \ - 1 | d
 //-                 - - - - | q
 //-
-module \$_DFFSR_NPN_ (C, S, R, D, Q);
-input C, S, R, D;
+module \$_DFFE_NP0P_ (D, C, R, E, Q);
+input D, C, R, E;
 output reg Q;
-always @(negedge C, posedge S, negedge R) begin
-	if (R == 0)
+always @(negedge C or posedge R) begin
+	if (R == 1)
 		Q <= 0;
-	else if (S == 1)
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_NP1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set and negative
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 1 - | 1
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_NP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or posedge R) begin
+	if (R == 1)
 		Q <= 1;
-	else
+	else if (E == 0)
 		Q <= D;
 end
 endmodule
 
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
-//-     $_DFFSR_NPP_ (C, S, R, D, Q)
+//-     $_DFFE_NP1P_ (D, C, R, E, Q)
 //-
 //- A negative edge D-type flip-flop with positive polarity set and positive
-//- polarity reset.
+//- polarity clock enable.
 //-
-//- Truth table:    C S R D | Q
+//- Truth table:    D C R E | Q
 //-                ---------+---
-//-                 - - 1 - | 0
-//-                 - 1 - - | 1
-//-                 \ - - d | d
+//-                 - - 1 - | 1
+//-                 d \ - 1 | d
 //-                 - - - - | q
 //-
-module \$_DFFSR_NPP_ (C, S, R, D, Q);
-input C, S, R, D;
+module \$_DFFE_NP1P_ (D, C, R, E, Q);
+input D, C, R, E;
 output reg Q;
-always @(negedge C, posedge S, posedge R) begin
+always @(negedge C or posedge R) begin
 	if (R == 1)
-		Q <= 0;
-	else if (S == 1)
 		Q <= 1;
-	else
+	else if (E == 1)
 		Q <= D;
 end
 endmodule
 
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
-//-     $_DFFSR_PNN_ (C, S, R, D, Q)
+//-     $_DFFE_PN0N_ (D, C, R, E, Q)
 //-
-//- A positive edge D-type flip-flop with negative polarity set and negative
-//- polarity reset.
+//- A positive edge D-type flip-flop with negative polarity reset and negative
+//- polarity clock enable.
 //-
-//- Truth table:    C S R D | Q
+//- Truth table:    D C R E | Q
 //-                ---------+---
 //-                 - - 0 - | 0
-//-                 - 0 - - | 1
-//-                 / - - d | d
+//-                 d / - 0 | d
 //-                 - - - - | q
 //-
-module \$_DFFSR_PNN_ (C, S, R, D, Q);
-input C, S, R, D;
+module \$_DFFE_PN0N_ (D, C, R, E, Q);
+input D, C, R, E;
 output reg Q;
-always @(posedge C, negedge S, negedge R) begin
+always @(posedge C or negedge R) begin
 	if (R == 0)
 		Q <= 0;
-	else if (S == 0)
-		Q <= 1;
-	else
+	else if (E == 0)
 		Q <= D;
 end
 endmodule
 
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
-//-     $_DFFSR_PNP_ (C, S, R, D, Q)
+//-     $_DFFE_PN0P_ (D, C, R, E, Q)
 //-
-//- A positive edge D-type flip-flop with negative polarity set and positive
-//- polarity reset.
+//- A positive edge D-type flip-flop with negative polarity reset and positive
+//- polarity clock enable.
 //-
-//- Truth table:    C S R D | Q
+//- Truth table:    D C R E | Q
 //-                ---------+---
-//-                 - - 1 - | 0
-//-                 - 0 - - | 1
-//-                 / - - d | d
+//-                 - - 0 - | 0
+//-                 d / - 1 | d
 //-                 - - - - | q
 //-
-module \$_DFFSR_PNP_ (C, S, R, D, Q);
-input C, S, R, D;
+module \$_DFFE_PN0P_ (D, C, R, E, Q);
+input D, C, R, E;
 output reg Q;
-always @(posedge C, negedge S, posedge R) begin
-	if (R == 1)
+always @(posedge C or negedge R) begin
+	if (R == 0)
 		Q <= 0;
-	else if (S == 0)
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_PN1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set and negative
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 0 - | 1
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_PN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or negedge R) begin
+	if (R == 0)
 		Q <= 1;
-	else
+	else if (E == 0)
 		Q <= D;
 end
 endmodule
 
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
-//-     $_DFFSR_PPN_ (C, S, R, D, Q)
+//-     $_DFFE_PN1P_ (D, C, R, E, Q)
 //-
-//- A positive edge D-type flip-flop with positive polarity set and negative
-//- polarity reset.
+//- A positive edge D-type flip-flop with negative polarity set and positive
+//- polarity clock enable.
 //-
-//- Truth table:    C S R D | Q
+//- Truth table:    D C R E | Q
 //-                ---------+---
-//-                 - - 0 - | 0
-//-                 - 1 - - | 1
-//-                 / - - d | d
+//-                 - - 0 - | 1
+//-                 d / - 1 | d
 //-                 - - - - | q
 //-
-module \$_DFFSR_PPN_ (C, S, R, D, Q);
-input C, S, R, D;
+module \$_DFFE_PN1P_ (D, C, R, E, Q);
+input D, C, R, E;
 output reg Q;
-always @(posedge C, posedge S, negedge R) begin
+always @(posedge C or negedge R) begin
 	if (R == 0)
-		Q <= 0;
-	else if (S == 1)
 		Q <= 1;
-	else
+	else if (E == 1)
 		Q <= D;
 end
 endmodule
 
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
-//-     $_DFFSR_PPP_ (C, S, R, D, Q)
+//-     $_DFFE_PP0N_ (D, C, R, E, Q)
 //-
-//- A positive edge D-type flip-flop with positive polarity set and positive
-//- polarity reset.
+//- A positive edge D-type flip-flop with positive polarity reset and negative
+//- polarity clock enable.
 //-
-//- Truth table:    C S R D | Q
+//- Truth table:    D C R E | Q
 //-                ---------+---
 //-                 - - 1 - | 0
-//-                 - 1 - - | 1
-//-                 / - - d | d
+//-                 d / - 0 | d
 //-                 - - - - | q
 //-
-module \$_DFFSR_PPP_ (C, S, R, D, Q);
-input C, S, R, D;
+module \$_DFFE_PP0N_ (D, C, R, E, Q);
+input D, C, R, E;
 output reg Q;
-always @(posedge C, posedge S, posedge R) begin
+always @(posedge C or posedge R) begin
 	if (R == 1)
 		Q <= 0;
-	else if (S == 1)
-		Q <= 1;
-	else
+	else if (E == 0)
 		Q <= D;
 end
 endmodule
 
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
-//-     $_DLATCH_N_ (E, D, Q)
+//-     $_DFFE_PP0P_ (D, C, R, E, Q)
 //-
-//- A negative enable D-type latch.
+//- A positive edge D-type flip-flop with positive polarity reset and positive
+//- polarity clock enable.
 //-
-//- Truth table:    E D | Q
-//-                -----+---
-//-                 0 d | d
-//-                 - - | q
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 1 - | 0
+//-                 d / - 1 | d
+//-                 - - - - | q
 //-
-module \$_DLATCH_N_ (E, D, Q);
-input E, D;
+module \$_DFFE_PP0P_ (D, C, R, E, Q);
+input D, C, R, E;
 output reg Q;
-always @* begin
-	if (E == 0)
+always @(posedge C or posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (E == 1)
 		Q <= D;
 end
 endmodule
 
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
-//-     $_DLATCH_P_ (E, D, Q)
+//-     $_DFFE_PP1N_ (D, C, R, E, Q)
 //-
-//- A positive enable D-type latch.
+//- A positive edge D-type flip-flop with positive polarity set and negative
+//- polarity clock enable.
 //-
-//- Truth table:    E D | Q
-//-                -----+---
-//-                 1 d | d
-//-                 - - | q
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 1 - | 1
+//-                 d / - 0 | d
+//-                 - - - - | q
 //-
-module \$_DLATCH_P_ (E, D, Q);
-input E, D;
+module \$_DFFE_PP1N_ (D, C, R, E, Q);
+input D, C, R, E;
 output reg Q;
-always @* begin
-	if (E == 1)
+always @(posedge C or posedge R) begin
+	if (R == 1)
+		Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_PP1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set and positive
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 1 - | 1
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_PP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or posedge R) begin
+	if (R == 1)
+		Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSR_NNN_ (C, S, R, D, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set and negative
+//- polarity reset.
+//-
+//- Truth table:    C S R D | Q
+//-                ---------+---
+//-                 - - 0 - | 0
+//-                 - 0 - - | 1
+//-                 \ - - d | d
+//-                 - - - - | q
+//-
+module \$_DFFSR_NNN_ (C, S, R, D, Q);
+input C, S, R, D;
+output reg Q;
+always @(negedge C, negedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSR_NNP_ (C, S, R, D, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set and positive
+//- polarity reset.
+//-
+//- Truth table:    C S R D | Q
+//-                ---------+---
+//-                 - - 1 - | 0
+//-                 - 0 - - | 1
+//-                 \ - - d | d
+//-                 - - - - | q
+//-
+module \$_DFFSR_NNP_ (C, S, R, D, Q);
+input C, S, R, D;
+output reg Q;
+always @(negedge C, negedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSR_NPN_ (C, S, R, D, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set and negative
+//- polarity reset.
+//-
+//- Truth table:    C S R D | Q
+//-                ---------+---
+//-                 - - 0 - | 0
+//-                 - 1 - - | 1
+//-                 \ - - d | d
+//-                 - - - - | q
+//-
+module \$_DFFSR_NPN_ (C, S, R, D, Q);
+input C, S, R, D;
+output reg Q;
+always @(negedge C, posedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSR_NPP_ (C, S, R, D, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set and positive
+//- polarity reset.
+//-
+//- Truth table:    C S R D | Q
+//-                ---------+---
+//-                 - - 1 - | 0
+//-                 - 1 - - | 1
+//-                 \ - - d | d
+//-                 - - - - | q
+//-
+module \$_DFFSR_NPP_ (C, S, R, D, Q);
+input C, S, R, D;
+output reg Q;
+always @(negedge C, posedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSR_PNN_ (C, S, R, D, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set and negative
+//- polarity reset.
+//-
+//- Truth table:    C S R D | Q
+//-                ---------+---
+//-                 - - 0 - | 0
+//-                 - 0 - - | 1
+//-                 / - - d | d
+//-                 - - - - | q
+//-
+module \$_DFFSR_PNN_ (C, S, R, D, Q);
+input C, S, R, D;
+output reg Q;
+always @(posedge C, negedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSR_PNP_ (C, S, R, D, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set and positive
+//- polarity reset.
+//-
+//- Truth table:    C S R D | Q
+//-                ---------+---
+//-                 - - 1 - | 0
+//-                 - 0 - - | 1
+//-                 / - - d | d
+//-                 - - - - | q
+//-
+module \$_DFFSR_PNP_ (C, S, R, D, Q);
+input C, S, R, D;
+output reg Q;
+always @(posedge C, negedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSR_PPN_ (C, S, R, D, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set and negative
+//- polarity reset.
+//-
+//- Truth table:    C S R D | Q
+//-                ---------+---
+//-                 - - 0 - | 0
+//-                 - 1 - - | 1
+//-                 / - - d | d
+//-                 - - - - | q
+//-
+module \$_DFFSR_PPN_ (C, S, R, D, Q);
+input C, S, R, D;
+output reg Q;
+always @(posedge C, posedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSR_PPP_ (C, S, R, D, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set and positive
+//- polarity reset.
+//-
+//- Truth table:    C S R D | Q
+//-                ---------+---
+//-                 - - 1 - | 0
+//-                 - 1 - - | 1
+//-                 / - - d | d
+//-                 - - - - | q
+//-
+module \$_DFFSR_PPP_ (C, S, R, D, Q);
+input C, S, R, D;
+output reg Q;
+always @(posedge C, posedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_NNNN_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set, negative
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 0 - - | 0
+//-                 - 0 - - - | 1
+//-                 \ - - 0 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_NNNN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, negedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+        else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_NNNP_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set, negative
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 0 - - | 0
+//-                 - 0 - - - | 1
+//-                 \ - - 1 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_NNNP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, negedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+        else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_NNPN_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set, positive
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 1 - - | 0
+//-                 - 0 - - - | 1
+//-                 \ - - 0 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_NNPN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, negedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+        else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_NNPP_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set, positive
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 1 - - | 0
+//-                 - 0 - - - | 1
+//-                 \ - - 1 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_NNPP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, negedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+        else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_NPNN_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set, negative
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 0 - - | 0
+//-                 - 1 - - - | 1
+//-                 \ - - 0 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_NPNN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, posedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+        else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_NPNP_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set, negative
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 0 - - | 0
+//-                 - 1 - - - | 1
+//-                 \ - - 1 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_NPNP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, posedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+        else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_NPPN_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set, positive
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 1 - - | 0
+//-                 - 1 - - - | 1
+//-                 \ - - 0 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_NPPN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, posedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+        else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_NPPP_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set, positive
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 1 - - | 0
+//-                 - 1 - - - | 1
+//-                 \ - - 1 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_NPPP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, posedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+        else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_PNNN_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set, negative
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 0 - - | 0
+//-                 - 0 - - - | 1
+//-                 / - - 0 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_PNNN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, negedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+        else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_PNNP_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set, negative
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 0 - - | 0
+//-                 - 0 - - - | 1
+//-                 / - - 1 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_PNNP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, negedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+        else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_PNPN_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set, positive
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 1 - - | 0
+//-                 - 0 - - - | 1
+//-                 / - - 0 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_PNPN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, negedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+        else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_PNPP_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set, positive
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 1 - - | 0
+//-                 - 0 - - - | 1
+//-                 / - - 1 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_PNPP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, negedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+        else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_PPNN_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set, negative
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 0 - - | 0
+//-                 - 1 - - - | 1
+//-                 / - - 0 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_PPNN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, posedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+        else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_PPNP_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set, negative
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 0 - - | 0
+//-                 - 1 - - - | 1
+//-                 / - - 1 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_PPNP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, posedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+        else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_PPPN_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set, positive
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 1 - - | 0
+//-                 - 1 - - - | 1
+//-                 / - - 0 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_PPPN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, posedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+        else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_PPPP_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set, positive
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 1 - - | 0
+//-                 - 1 - - - | 1
+//-                 / - - 1 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_PPPP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, posedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+        else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFF_NN0_ (D, C, R, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset.
+//-
+//- Truth table:    D C R | Q
+//-                -------+---
+//-                 - \ 0 | 0
+//-                 d \ - | d
+//-                 - - - | q
+//-
+module \$_SDFF_NN0_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(negedge C) begin
+	if (R == 0)
+		Q <= 0;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFF_NN1_ (D, C, R, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set.
+//-
+//- Truth table:    D C R | Q
+//-                -------+---
+//-                 - \ 0 | 1
+//-                 d \ - | d
+//-                 - - - | q
+//-
+module \$_SDFF_NN1_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(negedge C) begin
+	if (R == 0)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFF_NP0_ (D, C, R, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset.
+//-
+//- Truth table:    D C R | Q
+//-                -------+---
+//-                 - \ 1 | 0
+//-                 d \ - | d
+//-                 - - - | q
+//-
+module \$_SDFF_NP0_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(negedge C) begin
+	if (R == 1)
+		Q <= 0;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFF_NP1_ (D, C, R, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set.
+//-
+//- Truth table:    D C R | Q
+//-                -------+---
+//-                 - \ 1 | 1
+//-                 d \ - | d
+//-                 - - - | q
+//-
+module \$_SDFF_NP1_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(negedge C) begin
+	if (R == 1)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFF_PN0_ (D, C, R, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset.
+//-
+//- Truth table:    D C R | Q
+//-                -------+---
+//-                 - / 0 | 0
+//-                 d / - | d
+//-                 - - - | q
+//-
+module \$_SDFF_PN0_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(posedge C) begin
+	if (R == 0)
+		Q <= 0;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFF_PN1_ (D, C, R, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set.
+//-
+//- Truth table:    D C R | Q
+//-                -------+---
+//-                 - / 0 | 1
+//-                 d / - | d
+//-                 - - - | q
+//-
+module \$_SDFF_PN1_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(posedge C) begin
+	if (R == 0)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFF_PP0_ (D, C, R, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset.
+//-
+//- Truth table:    D C R | Q
+//-                -------+---
+//-                 - / 1 | 0
+//-                 d / - | d
+//-                 - - - | q
+//-
+module \$_SDFF_PP0_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(posedge C) begin
+	if (R == 1)
+		Q <= 0;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFF_PP1_ (D, C, R, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set.
+//-
+//- Truth table:    D C R | Q
+//-                -------+---
+//-                 - / 1 | 1
+//-                 d / - | d
+//-                 - - - | q
+//-
+module \$_SDFF_PP1_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(posedge C) begin
+	if (R == 1)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_NN0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 0 - | 0
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_NN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (R == 0)
+		Q <= 0;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_NN0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 0 - | 0
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_NN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (R == 0)
+		Q <= 0;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_NN1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set and negative
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 0 - | 1
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_NN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (R == 0)
+		Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_NN1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set and positive
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 0 - | 1
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_NN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (R == 0)
+		Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_NP0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 1 - | 0
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_NP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (R == 1)
+		Q <= 0;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_NP0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 1 - | 0
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_NP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (R == 1)
+		Q <= 0;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_NP1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set and negative
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 1 - | 1
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_NP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (R == 1)
+		Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_NP1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set and positive
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 1 - | 1
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_NP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (R == 1)
+		Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_PN0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 0 - | 0
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_PN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (R == 0)
+		Q <= 0;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_PN0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 0 - | 0
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_PN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (R == 0)
+		Q <= 0;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_PN1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set and negative
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 0 - | 1
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_PN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (R == 0)
+		Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_PN1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set and positive
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 0 - | 1
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_PN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (R == 0)
+		Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_PP0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 1 - | 0
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_PP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (R == 1)
+		Q <= 0;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_PP0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 1 - | 0
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_PP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (R == 1)
+		Q <= 0;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_PP1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set and negative
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 1 - | 1
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_PP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (R == 1)
+		Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_PP1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set and positive
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 1 - | 1
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_PP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (R == 1)
+		Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_NN0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 0 0 | 0
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_NN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (E == 0) begin
+		if (R == 0)
+			Q <= 0;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_NN0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 0 1 | 0
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_NN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (E == 1) begin
+		if (R == 0)
+			Q <= 0;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_NN1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 0 0 | 1
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_NN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (E == 0) begin
+		if (R == 0)
+			Q <= 1;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_NN1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 0 1 | 1
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_NN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (E == 1) begin
+		if (R == 0)
+			Q <= 1;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_NP0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 1 0 | 0
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_NP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (E == 0) begin
+		if (R == 1)
+			Q <= 0;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_NP0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 1 1 | 0
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_NP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (E == 1) begin
+		if (R == 1)
+			Q <= 0;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_NP1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 1 0 | 1
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_NP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (E == 0) begin
+		if (R == 1)
+			Q <= 1;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_NP1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 1 1 | 1
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_NP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (E == 1) begin
+		if (R == 1)
+			Q <= 1;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_PN0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 0 0 | 0
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_PN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (E == 0) begin
+		if (R == 0)
+			Q <= 0;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_PN0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 0 1 | 0
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_PN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (E == 1) begin
+		if (R == 0)
+			Q <= 0;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_PN1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 0 0 | 1
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_PN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (E == 0) begin
+		if (R == 0)
+			Q <= 1;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_PN1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 0 1 | 1
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_PN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (E == 1) begin
+		if (R == 0)
+			Q <= 1;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_PP0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 1 0 | 0
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_PP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (E == 0) begin
+		if (R == 1)
+			Q <= 0;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_PP0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 1 1 | 0
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_PP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (E == 1) begin
+		if (R == 1)
+			Q <= 0;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_PP1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 1 0 | 1
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_PP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (E == 0) begin
+		if (R == 1)
+			Q <= 1;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_PP1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 1 1 | 1
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_PP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (E == 1) begin
+		if (R == 1)
+			Q <= 1;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DLATCH_N_ (E, D, Q)
+//-
+//- A negative enable D-type latch.
+//-
+//- Truth table:    E D | Q
+//-                -----+---
+//-                 0 d | d
+//-                 - - | q
+//-
+module \$_DLATCH_N_ (E, D, Q);
+input E, D;
+output reg Q;
+always @* begin
+	if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DLATCH_P_ (E, D, Q)
+//-
+//- A positive enable D-type latch.
+//-
+//- Truth table:    E D | Q
+//-                -----+---
+//-                 1 d | d
+//-                 - - | q
+//-
+module \$_DLATCH_P_ (E, D, Q);
+input E, D;
+output reg Q;
+always @* begin
+	if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DLATCH_NN0_ (E, R, D, Q)
+//-
+//- A negative enable D-type latch with negative polarity reset.
+//-
+//- Truth table:    E R D | Q
+//-                -------+---
+//-                 - 0 - | 0
+//-                 0 - d | d
+//-                 - - - | q
+//-
+module \$_DLATCH_NN0_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+	if (R == 0)
+                Q <= 0;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DLATCH_NN1_ (E, R, D, Q)
+//-
+//- A negative enable D-type latch with negative polarity set.
+//-
+//- Truth table:    E R D | Q
+//-                -------+---
+//-                 - 0 - | 1
+//-                 0 - d | d
+//-                 - - - | q
+//-
+module \$_DLATCH_NN1_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+	if (R == 0)
+                Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DLATCH_NP0_ (E, R, D, Q)
+//-
+//- A negative enable D-type latch with positive polarity reset.
+//-
+//- Truth table:    E R D | Q
+//-                -------+---
+//-                 - 1 - | 0
+//-                 0 - d | d
+//-                 - - - | q
+//-
+module \$_DLATCH_NP0_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+	if (R == 0)
+                Q <= 0;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DLATCH_NP1_ (E, R, D, Q)
+//-
+//- A negative enable D-type latch with positive polarity set.
+//-
+//- Truth table:    E R D | Q
+//-                -------+---
+//-                 - 1 - | 1
+//-                 0 - d | d
+//-                 - - - | q
+//-
+module \$_DLATCH_NP1_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+	if (R == 0)
+                Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DLATCH_PN0_ (E, R, D, Q)
+//-
+//- A positive enable D-type latch with negative polarity reset.
+//-
+//- Truth table:    E R D | Q
+//-                -------+---
+//-                 - 0 - | 0
+//-                 1 - d | d
+//-                 - - - | q
+//-
+module \$_DLATCH_PN0_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+	if (R == 1)
+                Q <= 0;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DLATCH_PN1_ (E, R, D, Q)
+//-
+//- A positive enable D-type latch with negative polarity set.
+//-
+//- Truth table:    E R D | Q
+//-                -------+---
+//-                 - 0 - | 1
+//-                 1 - d | d
+//-                 - - - | q
+//-
+module \$_DLATCH_PN1_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+	if (R == 1)
+                Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DLATCH_PP0_ (E, R, D, Q)
+//-
+//- A positive enable D-type latch with positive polarity reset.
+//-
+//- Truth table:    E R D | Q
+//-                -------+---
+//-                 - 1 - | 0
+//-                 1 - d | d
+//-                 - - - | q
+//-
+module \$_DLATCH_PP0_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+	if (R == 1)
+                Q <= 0;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DLATCH_PP1_ (E, R, D, Q)
+//-
+//- A positive enable D-type latch with positive polarity set.
+//-
+//- Truth table:    E R D | Q
+//-                -------+---
+//-                 - 1 - | 1
+//-                 1 - d | d
+//-                 - - - | q
+//-
+module \$_DLATCH_PP1_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+	if (R == 1)
+                Q <= 1;
+	else if (E == 1)
 		Q <= D;
 end
 endmodule
-- 
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