From c77b7343d0412a009436a57764d907e2ae332da2 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Fri, 21 Oct 2022 15:41:20 +0200 Subject: Consistent $mux undef handling * Change simlib's $mux cell to use the ternary operator as $_MUX_ already does * Stop opt_expr -keepdc from changing S=x to S=0 * Change const eval of $mux and $pmux to match the updated simlib (fixes sim) * The sat behavior of $mux already matches the updated simlib The verilog frontend uses $mux for the ternary operators and this changes all interpreations of the $mux cell (that I found) to match the verilog simulation behavior for the ternary operator. For 'if' and 'case' expressions the frontend may also use $mux but uses $eqx if the verilog simulation behavior is requested with the '-ifx' option. For $pmux there is a remaining mismatch between the sat behavior and the simlib behavior. Resolving this requires more discussion, as the $pmux cell does not directly correspond to a specific verilog construct. --- techlibs/common/simlib.v | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'techlibs/common/simlib.v') diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index ab9bd7e1d..2fd75372d 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1282,10 +1282,7 @@ input S; output reg [WIDTH-1:0] Y; always @* begin - if (S) - Y = B; - else - Y = A; + assign Y = S ? B : A; end endmodule -- cgit v1.2.3