From 71dfbf33b292b6920ff1bab308c0c10b737bf763 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= Date: Thu, 2 Jun 2022 17:15:28 +0200 Subject: Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}. --- techlibs/common/synth.cc | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'techlibs/common/synth.cc') diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 79e5933e0..63395c368 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -81,6 +81,11 @@ struct SynthPass : public ScriptPass log(" -flowmap\n"); log(" use FlowMap LUT techmapping instead of ABC\n"); log("\n"); + log(" -no-rw-check\n"); + log(" marks all recognized read ports as \"return don't-care value on\n"); + log(" read/write collision\" (same result as setting the no_rw_check\n"); + log(" attribute on all memories).\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -175,6 +180,10 @@ struct SynthPass : public ScriptPass flowmap = true; continue; } + if (args[argidx] == "-no-rw-check") { + memory_opts += " -no-rw-check"; + continue; + } break; } extra_args(args, argidx, design); -- cgit v1.2.3