From 6c00704a5ef09be46b1f05e2be477e493f37dd38 Mon Sep 17 00:00:00 2001 From: Larry Doolittle Date: Fri, 14 Aug 2015 13:23:01 -0700 Subject: Another block of spelling fixes Smaller this time --- techlibs/common/simcells.v | 2 +- techlibs/common/simlib.v | 4 ++-- techlibs/common/techmap.v | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'techlibs/common') diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index 669706209..9a820f71c 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -19,7 +19,7 @@ * * The internal logic cell simulation library. * - * This verilog library contains simple simulation models for the internal + * This Verilog library contains simple simulation models for the internal * logic cells ($_NOT_ , $_AND_ , ...) that are generated by the default technology * mapper (see "techmap.v" in this directory) and expected by the "abc" pass. * diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 9de71e6f9..275c469b8 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -19,7 +19,7 @@ * * The Simulation Library. * - * This verilog library contains simple simulation models for the internal + * This Verilog library contains simple simulation models for the internal * cells ($not, ...) generated by the frontends and used in most passes. * * This library can be used to verify the internal netlists as generated @@ -1163,7 +1163,7 @@ input A, EN; `ifndef SIMLIB_NOCHECKS always @* begin if (A !== 1'b1 && EN === 1'b1) begin - $display("Assertation %m failed!"); + $display("Assertion %m failed!"); $stop; end end diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index e4974789e..44467203e 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -19,7 +19,7 @@ * * The internal logic cell technology mapper. * - * This verilog library contains the mapping of internal cells (e.g. $not with + * This Verilog library contains the mapping of internal cells (e.g. $not with * variable bit width) to the internal logic cells (such as the single bit $_NOT_ * gate). Usually this logic network is then mapped to the actual technology * using e.g. the "abc" pass. -- cgit v1.2.3