From c38283dbd033ba95554600bbaa850de707ab2a78 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 2 Sep 2014 17:48:41 +0200
Subject: Small bug fixes in $not, $neg, and $shiftx models

---
 techlibs/common/simlib.v | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 3c931c813..09ffa9a68 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -108,13 +108,12 @@ parameter Y_WIDTH = 0;
 
 input [A_WIDTH-1:0] A;
 output [Y_WIDTH-1:0] Y;
-wire [Y_WIDTH-1:0] tmp;
 
 generate
 	if (A_SIGNED) begin:BLOCK1
-		assign tmp = $signed(A), Y = -tmp;
+		assign Y = -$signed(A);
 	end else begin:BLOCK2
-		assign tmp = A, Y = -tmp;
+		assign Y = -A;
 	end
 endgenerate
 
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