From 6a0682f5a0148949beacad0eb93ec5b754bf29cd Mon Sep 17 00:00:00 2001 From: "R. Ou" Date: Sun, 16 Feb 2020 20:25:46 -0800 Subject: coolrunner2: Separate and improve buffer cell insertion pass The new pass will contain all of the logic for inserting "passthrough" product term and XOR cells as appropriate for the architecture. For example, this commit fixes connecting an input pin directly to another output pin with no logic in between. --- techlibs/coolrunner2/coolrunner2_sop.cc | 54 --------------------------------- 1 file changed, 54 deletions(-) (limited to 'techlibs/coolrunner2/coolrunner2_sop.cc') diff --git a/techlibs/coolrunner2/coolrunner2_sop.cc b/techlibs/coolrunner2/coolrunner2_sop.cc index de0cbb29d..49ae8e21a 100644 --- a/techlibs/coolrunner2/coolrunner2_sop.cc +++ b/techlibs/coolrunner2/coolrunner2_sop.cc @@ -248,60 +248,6 @@ struct Coolrunner2SopPass : public Pass { } } - // In some cases we can get a FF feeding straight into an FF. This is not possible, so we need to insert - // some AND/XOR cells in the middle to make it actually work. - - // Find all the FF outputs - pool sig_fed_by_ff; - for (auto cell : module->selected_cells()) - { - if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N", - "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE")) - { - auto output = sigmap(cell->getPort("\\Q")[0]); - sig_fed_by_ff.insert(output); - } - } - - // Look at all the FF inputs - for (auto cell : module->selected_cells()) - { - if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N", - "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE")) - { - SigBit input; - if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP")) - input = sigmap(cell->getPort("\\T")[0]); - else - input = sigmap(cell->getPort("\\D")[0]); - - if (sig_fed_by_ff[input]) - { - printf("Buffering input to \"%s\"\n", cell->name.c_str()); - - auto and_to_xor_wire = module->addWire(NEW_ID); - auto xor_to_ff_wire = module->addWire(NEW_ID); - - auto and_cell = module->addCell(NEW_ID, "\\ANDTERM"); - and_cell->setParam("\\TRUE_INP", 1); - and_cell->setParam("\\COMP_INP", 0); - and_cell->setPort("\\OUT", and_to_xor_wire); - and_cell->setPort("\\IN", input); - and_cell->setPort("\\IN_B", SigSpec()); - - auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR"); - xor_cell->setParam("\\INVERT_OUT", false); - xor_cell->setPort("\\IN_PTC", and_to_xor_wire); - xor_cell->setPort("\\OUT", xor_to_ff_wire); - - if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP")) - cell->setPort("\\T", xor_to_ff_wire); - else - cell->setPort("\\D", xor_to_ff_wire); - } - } - } - // Actually do the removal now that we aren't iterating for (auto cell : cells_to_remove) { -- cgit v1.2.3