From 71dfbf33b292b6920ff1bab308c0c10b737bf763 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= Date: Thu, 2 Jun 2022 17:15:28 +0200 Subject: Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}. --- techlibs/ecp5/synth_ecp5.cc | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) (limited to 'techlibs/ecp5/synth_ecp5.cc') diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 8c7ea5b39..f2dc534f9 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -103,6 +103,11 @@ struct SynthEcp5Pass : public ScriptPass log(" -nodsp\n"); log(" do not map multipliers to MULT18X18D\n"); log("\n"); + log(" -no-rw-check\n"); + log(" marks all recognized read ports as \"return don't-care value on\n"); + log(" read/write collision\" (same result as setting the no_rw_check\n"); + log(" attribute on all memories).\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -110,7 +115,7 @@ struct SynthEcp5Pass : public ScriptPass } string top_opt, blif_file, edif_file, json_file; - bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, nodsp, vpr; + bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, nodsp, vpr, no_rw_check; void clear_flags() override { @@ -131,6 +136,7 @@ struct SynthEcp5Pass : public ScriptPass vpr = false; abc9 = false; nodsp = false; + no_rw_check = false; } void execute(std::vector args, RTLIL::Design *design) override @@ -221,6 +227,10 @@ struct SynthEcp5Pass : public ScriptPass nodsp = true; continue; } + if (args[argidx] == "-no-rw-check") { + no_rw_check = true; + continue; + } break; } extra_args(args, argidx, design); @@ -241,6 +251,12 @@ struct SynthEcp5Pass : public ScriptPass void script() override { + std::string no_rw_check_opt = ""; + if (no_rw_check) + no_rw_check_opt = " -no-rw-check"; + if (help_mode) + no_rw_check_opt = " [-no-rw-check]"; + if (check_label("begin")) { run("read_verilog -lib -specify +/ecp5/cells_sim.v +/ecp5/cells_bb.v"); @@ -273,7 +289,7 @@ struct SynthEcp5Pass : public ScriptPass } run("alumacc"); run("opt"); - run("memory -nomap"); + run("memory -nomap" + no_rw_check_opt); run("opt_clean"); } -- cgit v1.2.3