From 98c9ea605b5cb2eb540ae5b804a18f8921f0bc46 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 6 Dec 2019 17:05:02 -0800
Subject: techmap/aigmap of whiteboxes to occur before abc9 instead of in
 write_xaiger

---
 techlibs/ecp5/synth_ecp5.cc | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 4cbb56ea1..b099c25d3 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -312,6 +312,11 @@ struct SynthEcp5Pass : public ScriptPass
 			run("techmap " + techmap_args);
 
 			if (abc9) {
+				run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
+				run("wbflip @abc9_boxes");
+				run("techmap -autoproc @abc9_boxes");
+				run("aigmap @abc9_boxes");
+				run("wbflip @abc9_boxes");
 				run("read_verilog -icells -lib +/ecp5/abc9_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
-- 
cgit v1.2.3


From 184c0e796a0e6870c025808b1902da5f3771b721 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Sat, 7 Dec 2019 13:04:36 +0000
Subject: ecp5: Add support for mapping PRLD FFs

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_map.v   | 15 +++++++++++++++
 techlibs/ecp5/synth_ecp5.cc | 17 +++++++++++++----
 2 files changed, 28 insertions(+), 4 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 71ae9237b..10e89a3e0 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -47,6 +47,21 @@ module  \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .
 module  \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 
+`ifdef ASYNC_PRLD
+module  \$_DLATCH_N_ (input E, input D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.LSR(!E), .DI(1'b0), .M(D), .Q(Q)); endmodule
+module  \$_DLATCH_P_ (input E, input D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.LSR(E), .DI(1'b0), .M(D), .Q(Q)); endmodule
+
+module \$_DFFSR_NNN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || !R), .DI(D), .M(R), .Q(Q)); endmodule
+module \$_DFFSR_NNP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || R), .DI(D), .M(!R), .Q(Q)); endmodule
+module \$_DFFSR_NPN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || !R), .DI(D), .M(R), .Q(Q)); endmodule
+module \$_DFFSR_NPP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || R), .DI(D), .M(!R), .Q(Q)); endmodule
+
+module \$_DFFSR_PNN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || !R), .DI(D), .M(R), .Q(Q)); endmodule
+module \$_DFFSR_PNP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || R), .DI(D), .M(!R), .Q(Q)); endmodule
+module \$_DFFSR_PPN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || !R), .DI(D), .M(R), .Q(Q)); endmodule
+module \$_DFFSR_PPP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || R), .DI(D), .M(!R), .Q(Q)); endmodule
+`endif
+
 `include "cells_ff.vh"
 `include "cells_io.vh"
 
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 4cbb56ea1..b71bb2395 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -79,6 +79,9 @@ struct SynthEcp5Pass : public ScriptPass
 		log("    -nowidelut\n");
 		log("        do not use PFU muxes to implement LUTs larger than LUT4s\n");
 		log("\n");
+		log("    -asyncprld\n");
+		log("        use async PRLD mode to implement DLATCH and DFFSR (EXPERIMENTAL)\n");
+		log("\n");
 		log("    -abc2\n");
 		log("        run two passes of 'abc' for slightly improved logic density\n");
 		log("\n");
@@ -99,7 +102,7 @@ struct SynthEcp5Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file;
-	bool noccu2, nodffe, nobram, nolutram, nowidelut, flatten, retime, abc2, abc9, nodsp, vpr;
+	bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, retime, abc2, abc9, nodsp, vpr;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -112,6 +115,7 @@ struct SynthEcp5Pass : public ScriptPass
 		nobram = false;
 		nolutram = false;
 		nowidelut = false;
+		asyncprld = false;
 		flatten = true;
 		retime = false;
 		abc2 = false;
@@ -176,6 +180,10 @@ struct SynthEcp5Pass : public ScriptPass
 				nobram = true;
 				continue;
 			}
+			if (args[argidx] == "-asyncprld") {
+				asyncprld = true;
+				continue;
+			}
 			if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
 				nolutram = true;
 				continue;
@@ -292,7 +300,7 @@ struct SynthEcp5Pass : public ScriptPass
 			run("opt_clean");
 			if (!nodffe)
 				run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
-			run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
+			run(stringf("techmap -D NO_LUT %s -map +/ecp5/cells_map.v", help_mode ? "[-D ASYNC_PRLD]" : (asyncprld ? "-D ASYNC_PRLD" : "")));
 			run("opt_expr -undriven -mux_undef");
 			run("simplemap");
 			run("ecp5_ffinit");
@@ -306,10 +314,11 @@ struct SynthEcp5Pass : public ScriptPass
 			if (abc2 || help_mode) {
 				run("abc", "      (only if -abc2)");
 			}
-			std::string techmap_args = "-map +/ecp5/latches_map.v";
+			std::string techmap_args = asyncprld ? "" : "-map +/ecp5/latches_map.v";
 			if (abc9)
 				techmap_args += " -map +/ecp5/abc9_map.v -max_iter 1";
-			run("techmap " + techmap_args);
+			if (!asyncprld || abc9)
+				run("techmap " + techmap_args);
 
 			if (abc9) {
 				run("read_verilog -icells -lib +/ecp5/abc9_model.v");
-- 
cgit v1.2.3


From 10e82e103f7b95d5a50d2ac85bc8e07e4461e388 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 20 Dec 2019 12:05:45 -0800
Subject: Revert "Optimise write_xaiger"

---
 techlibs/ecp5/synth_ecp5.cc | 5 -----
 1 file changed, 5 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 16ff9c57a..b71bb2395 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -321,11 +321,6 @@ struct SynthEcp5Pass : public ScriptPass
 				run("techmap " + techmap_args);
 
 			if (abc9) {
-				run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
-				run("wbflip @abc9_boxes");
-				run("techmap -autoproc @abc9_boxes");
-				run("aigmap @abc9_boxes");
-				run("wbflip @abc9_boxes");
 				run("read_verilog -icells -lib +/ecp5/abc9_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
-- 
cgit v1.2.3


From 71906fab51c60d22ee5b145df0429287ab9d2d65 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 27 Dec 2019 16:57:08 -0800
Subject: Nitpick cleanup for ecp5

---
 techlibs/ecp5/cells_sim.v   | 12 ++----------
 techlibs/ecp5/synth_ecp5.cc |  2 +-
 2 files changed, 3 insertions(+), 11 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index f467218cc..0d3ec4e5b 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -1,5 +1,6 @@
 // ---------------------------------------
 
+(* lib_whitebox *)
 module LUT4(input A, B, C, D, output Z);
     parameter [15:0] INIT = 16'h0000;
     wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];
@@ -31,13 +32,8 @@ module CCU2C(
 
 	// First half
 	wire LUT4_0, LUT2_0;
-`ifdef _ABC
-	assign LUT4_0 = INIT0[{D0, C0, B0, A0}];
-	assign LUT2_0 = INIT0[{2'b00, B0, A0}];
-`else
 	LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
 	LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
-`endif
 	wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
 	assign S0 = LUT4_0 ^ gated_cin_0;
 
@@ -46,13 +42,8 @@ module CCU2C(
 
 	// Second half
 	wire LUT4_1, LUT2_1;
-`ifdef _ABC
-	assign LUT4_1 = INIT1[{D1, C1, B1, A1}];
-	assign LUT2_1 = INIT1[{2'b00, B1, A1}];
-`else
 	LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
 	LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
-`endif
 	wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
 	assign S1 = LUT4_1 ^ gated_cin_1;
 
@@ -209,6 +200,7 @@ endmodule
 
 // ---------------------------------------
 
+(* lib_whitebox *)
 module LUT2(input A, B, output Z);
     parameter [3:0] INIT = 4'h0;
     wire [1:0] s1 = B ?     INIT[ 3:2] :     INIT[1:0];
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index b71bb2395..a0ea6d1f9 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -230,7 +230,7 @@ struct SynthEcp5Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -D_ABC -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
+			run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}
 
-- 
cgit v1.2.3


From aa6d06c1b5b0083096ad547b0ad2600fcdc854f4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Dec 2019 12:09:53 -0800
Subject: Revert "Revert "synth_* with -retime option now calls abc with -D 1
 as well""

This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
---
 techlibs/ecp5/synth_ecp5.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index a0ea6d1f9..24e300fa8 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -290,7 +290,7 @@ struct SynthEcp5Pass : public ScriptPass
 			else
 				run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
 			if (retime || help_mode)
-				run("abc -dff", "(only if -retime)");
+				run("abc -dff -D 1", "(only if -retime)");
 		}
 
 		if (check_label("map_ffs"))
-- 
cgit v1.2.3


From 79448f9be035c88589b4e9c0de6b2bdc5acbd4df Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Dec 2019 12:11:45 -0800
Subject: Update doc that "-retime" calls abc with "-dff -D 1"

---
 techlibs/ecp5/synth_ecp5.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 24e300fa8..1ecb9cac3 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -62,7 +62,7 @@ struct SynthEcp5Pass : public ScriptPass
 		log("        do not flatten design before synthesis\n");
 		log("\n");
 		log("    -retime\n");
-		log("        run 'abc' with -dff option\n");
+		log("        run 'abc' with '-dff -D 1' options\n");
 		log("\n");
 		log("    -noccu2\n");
 		log("        do not use CCU2 cells in output netlist\n");
-- 
cgit v1.2.3


From 550310e2647c7aac1e49b79d9ff912436103062f Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 1 Jan 2020 12:30:00 +0000
Subject: Harmonize BRAM/LUTRAM descriptions across all of Yosys.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit:
  * renames all remaining instances of "DRAM" (which is ambiguous)
    to "LUTRAM" (which is not), finishing the work started in
    the commit 698ab9be;
  * renames memory rule files to brams.txt/lutrams.txt;
  * adds/renames script labels map_bram/map_lutram;
  * extracts where necessary script labels map_ffram and map_gates;
  * adds where necessary options -nobram/-nolutram.

The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.

Per architecture:
  * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
    :map_lutram, :map_ffram, :map_gates
  * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
  * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
    :map_gates
  * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
    rename -nodram→-nolutram (-nodram still recognized), rename
    :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
---
 techlibs/ecp5/Makefile.inc  |  4 ++--
 techlibs/ecp5/bram.txt      | 52 ---------------------------------------------
 techlibs/ecp5/brams.txt     | 52 +++++++++++++++++++++++++++++++++++++++++++++
 techlibs/ecp5/lutram.txt    | 17 ---------------
 techlibs/ecp5/lutrams.txt   | 17 +++++++++++++++
 techlibs/ecp5/synth_ecp5.cc |  4 ++--
 6 files changed, 73 insertions(+), 73 deletions(-)
 delete mode 100644 techlibs/ecp5/bram.txt
 create mode 100644 techlibs/ecp5/brams.txt
 delete mode 100644 techlibs/ecp5/lutram.txt
 create mode 100644 techlibs/ecp5/lutrams.txt

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 46463f510..2c33f23b9 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -8,9 +8,9 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_bb.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams_map.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutram.txt))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
diff --git a/techlibs/ecp5/bram.txt b/techlibs/ecp5/bram.txt
deleted file mode 100644
index 777ccaa2e..000000000
--- a/techlibs/ecp5/bram.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-bram $__ECP5_PDPW16KD
-  init 1
-
-  abits 9
-  dbits 36
-
-  groups 2
-  ports 1 1
-  wrmode 1 0
-  enable 4 1
-  transp 0 0
-  clocks 2 3
-  clkpol 2 3
-endbram
-
-bram $__ECP5_DP16KD
-  init 1
-
-  abits 10 @a10d18
-  dbits 18 @a10d18
-  abits 11 @a11d9
-  dbits 9  @a11d9
-  abits 12 @a12d4
-  dbits 4  @a12d4
-  abits 13 @a13d2
-  dbits 2  @a13d2
-  abits 14 @a14d1
-  dbits 1  @a14d1
-
-  groups 2
-  ports 1 1
-  wrmode 1 0
-  enable 2 1 @a10d18
-  enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
-  transp 0 2
-  clocks 2 3
-  clkpol 2 3
-endbram
-
-match $__ECP5_PDPW16KD
-  min bits 2048
-  min efficiency 5
-  shuffle_enable A
-  make_transp
-  or_next_if_better
-endmatch
-
-match $__ECP5_DP16KD
-  min bits 2048
-  min efficiency 5
-  shuffle_enable A
-endmatch
diff --git a/techlibs/ecp5/brams.txt b/techlibs/ecp5/brams.txt
new file mode 100644
index 000000000..777ccaa2e
--- /dev/null
+++ b/techlibs/ecp5/brams.txt
@@ -0,0 +1,52 @@
+bram $__ECP5_PDPW16KD
+  init 1
+
+  abits 9
+  dbits 36
+
+  groups 2
+  ports 1 1
+  wrmode 1 0
+  enable 4 1
+  transp 0 0
+  clocks 2 3
+  clkpol 2 3
+endbram
+
+bram $__ECP5_DP16KD
+  init 1
+
+  abits 10 @a10d18
+  dbits 18 @a10d18
+  abits 11 @a11d9
+  dbits 9  @a11d9
+  abits 12 @a12d4
+  dbits 4  @a12d4
+  abits 13 @a13d2
+  dbits 2  @a13d2
+  abits 14 @a14d1
+  dbits 1  @a14d1
+
+  groups 2
+  ports 1 1
+  wrmode 1 0
+  enable 2 1 @a10d18
+  enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
+  transp 0 2
+  clocks 2 3
+  clkpol 2 3
+endbram
+
+match $__ECP5_PDPW16KD
+  min bits 2048
+  min efficiency 5
+  shuffle_enable A
+  make_transp
+  or_next_if_better
+endmatch
+
+match $__ECP5_DP16KD
+  min bits 2048
+  min efficiency 5
+  shuffle_enable A
+endmatch
diff --git a/techlibs/ecp5/lutram.txt b/techlibs/ecp5/lutram.txt
deleted file mode 100644
index b94357429..000000000
--- a/techlibs/ecp5/lutram.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-bram $__TRELLIS_DPR16X4
-  init 1
-  abits 4
-  dbits 4
-  groups 2
-  ports  1 1
-  wrmode 0 1
-  enable 0 1
-  transp 0 0
-  clocks 0 1
-  clkpol 0 2
-endbram
-
-match $__TRELLIS_DPR16X4
-  make_outreg
-  min wports 1
-endmatch
diff --git a/techlibs/ecp5/lutrams.txt b/techlibs/ecp5/lutrams.txt
new file mode 100644
index 000000000..b94357429
--- /dev/null
+++ b/techlibs/ecp5/lutrams.txt
@@ -0,0 +1,17 @@
+bram $__TRELLIS_DPR16X4
+  init 1
+  abits 4
+  dbits 4
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 2
+endbram
+
+match $__TRELLIS_DPR16X4
+  make_outreg
+  min wports 1
+endmatch
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index a0ea6d1f9..3985da57a 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -266,13 +266,13 @@ struct SynthEcp5Pass : public ScriptPass
 
 		if (!nobram && check_label("map_bram", "(skip if -nobram)"))
 		{
-			run("memory_bram -rules +/ecp5/bram.txt");
+			run("memory_bram -rules +/ecp5/brams.txt");
 			run("techmap -map +/ecp5/brams_map.v");
 		}
 
 		if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
 		{
-			run("memory_bram -rules +/ecp5/lutram.txt");
+			run("memory_bram -rules +/ecp5/lutrams.txt");
 			run("techmap -map +/ecp5/lutrams_map.v");
 		}
 
-- 
cgit v1.2.3