From 55acf3120fa47bb95be8a6551738f4f9b1c70a21 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 18:59:03 -0700 Subject: ecp5 to use abc_map.v and _unmap.v --- techlibs/ecp5/Makefile.inc | 3 +++ techlibs/ecp5/abc_5g.box | 18 +++++++++--------- techlibs/ecp5/abc_map.v | 24 ++++++++++++++++++++++++ techlibs/ecp5/abc_model.v | 18 ++++++++++++++++++ techlibs/ecp5/abc_unmap.v | 25 +++++++++++++++++++++++++ techlibs/ecp5/cells_sim.v | 7 +++---- techlibs/ecp5/synth_ecp5.cc | 8 +++++++- 7 files changed, 89 insertions(+), 14 deletions(-) create mode 100644 techlibs/ecp5/abc_map.v create mode 100644 techlibs/ecp5/abc_model.v create mode 100644 techlibs/ecp5/abc_unmap.v (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index 73e18112f..cffd5c3a4 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -11,6 +11,9 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_map.v)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_unmap.v)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_model.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut)) diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box index c757d137d..66ebe196a 100644 --- a/techlibs/ecp5/abc_5g.box +++ b/techlibs/ecp5/abc_5g.box @@ -15,16 +15,16 @@ CCU2C 1 1 9 3 630 379 630 379 526 275 392 141 273 516 516 516 516 412 412 278 278 43 -# Box 2 : TRELLIS_DPR16X4 (16x4 dist ram) +# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram) # Outputs: DO0, DO1, DO2, DO3 -# name ID w/b ins outs -TRELLIS_DPR16X4 2 0 14 4 - -#DI0 DI1 DI2 DI3 RAD0 RAD1 RAD2 RAD3 WAD0 WAD1 WAD2 WAD3 WCK WRE -- - - - 141 379 275 379 - - - - - - -- - - - 141 379 275 379 - - - - - - -- - - - 141 379 275 379 - - - - - - -- - - - 141 379 275 379 - - - - - - +# name ID w/b ins outs +$__ABC_RAM16X2_COMB 2 0 8 4 + +#A0 A1 A2 A3 RAD0 RAD1 RAD2 RAD3 +0 0 0 0 141 379 275 379 +0 0 0 0 141 379 275 379 +0 0 0 0 141 379 275 379 +0 0 0 0 141 379 275 379 # Box 3 : PFUMX (MUX2) # Outputs: Z diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc_map.v new file mode 100644 index 000000000..e8187ed18 --- /dev/null +++ b/techlibs/ecp5/abc_map.v @@ -0,0 +1,24 @@ +// --------------------------------------- + +module TRELLIS_DPR16X4 ( + input [3:0] DI, + input [3:0] WAD, + input WRE, + input WCK, + input [3:0] RAD, + output [3:0] DO +); + parameter WCKMUX = "WCK"; + parameter WREMUX = "WRE"; + parameter [63:0] INITVAL = 64'h0000000000000000; + wire [3:0] \$DO ; + + \$__ABC_DPR16X4_SEQ #( + .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL) + ) _TECHMAP_REPLACE_ ( + .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK), + .RAD(RAD), .DO(\$DO ) + ); + + \$__ABC_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO)); +endmodule diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v new file mode 100644 index 000000000..4eb923cb1 --- /dev/null +++ b/techlibs/ecp5/abc_model.v @@ -0,0 +1,18 @@ +// --------------------------------------- + +(* abc_box_id=2 *) +module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y); +endmodule + +module \$__ABC_DPR16X4_SEQ ( + input [3:0] DI, + input [3:0] WAD, + input WRE, + input WCK, + input [3:0] RAD, + output [3:0] DO +); + parameter WCKMUX = "WCK"; + parameter WREMUX = "WRE"; + parameter [63:0] INITVAL = 64'h0000000000000000; +endmodule diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc_unmap.v new file mode 100644 index 000000000..0f918c202 --- /dev/null +++ b/techlibs/ecp5/abc_unmap.v @@ -0,0 +1,25 @@ +// --------------------------------------- + +module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y); + assign Y = A; +endmodule + +module \$__ABC_DPR16X4_SEQ ( + input [3:0] DI, + input [3:0] WAD, + input WRE, + input WCK, + input [3:0] RAD, + output [3:0] DO +); + parameter WCKMUX = "WCK"; + parameter WREMUX = "WRE"; + parameter [63:0] INITVAL = 64'h0000000000000000; + + TRELLIS_DPR16X4 #( + .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL) + ) _TECHMAP_REPLACE_ ( + .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK), + .RAD(RAD), .DO(DO) + ); +endmodule diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 2fcb0369e..f79a27312 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -107,11 +107,10 @@ module PFUMX (input ALUT, BLUT, C0, output Z); endmodule // --------------------------------------- -//(* abc_box_id=2 *) module TRELLIS_DPR16X4 ( - (* abc_scc_break *) input [3:0] DI, - (* abc_scc_break *) input [3:0] WAD, - (* abc_scc_break *) input WRE, + input [3:0] DI, + input [3:0] WAD, + input WRE, input WCK, input [3:0] RAD, output [3:0] DO diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 143d1f95c..93e1cd5b5 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -278,12 +278,18 @@ struct SynthEcp5Pass : public ScriptPass if (abc2 || help_mode) { run("abc", " (only if -abc2)"); } - run("techmap -map +/ecp5/latches_map.v"); + std::string techmap_args = "-map +/ecp5/latches_map.v"; + if (abc9) + techmap_args += " -map +/ecp5/abc_map.v"; + run("techmap " + techmap_args); + if (abc9) { + run("read_verilog -icells -lib +/ecp5/abc_model.v"); if (nowidelut) run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200"); else run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200"); + run("techmap -map +/ecp5/abc_unmap.v"); } else { if (nowidelut) run("abc -lut 4 -dress"); -- cgit v1.2.3 From d46dc9c5b4362c1e333979cbbac4f3567904fee5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 19:18:36 -0700 Subject: ecp5 to use -max_iter 1 --- techlibs/ecp5/abc_map.v | 2 +- techlibs/ecp5/cells_sim.v | 2 +- techlibs/ecp5/synth_ecp5.cc | 3 +-- 3 files changed, 3 insertions(+), 4 deletions(-) (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc_map.v index e8187ed18..ffd25f06d 100644 --- a/techlibs/ecp5/abc_map.v +++ b/techlibs/ecp5/abc_map.v @@ -13,7 +13,7 @@ module TRELLIS_DPR16X4 ( parameter [63:0] INITVAL = 64'h0000000000000000; wire [3:0] \$DO ; - \$__ABC_DPR16X4_SEQ #( + TRELLIS_DPR16X4 #( .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL) ) _TECHMAP_REPLACE_ ( .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK), diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index f79a27312..24de0c3c2 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -113,7 +113,7 @@ module TRELLIS_DPR16X4 ( input WRE, input WCK, input [3:0] RAD, - output [3:0] DO + /* (* abc_arrival= *) */ output [3:0] DO ); parameter WCKMUX = "WCK"; parameter WREMUX = "WRE"; diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 93e1cd5b5..b1d3160ba 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -280,11 +280,10 @@ struct SynthEcp5Pass : public ScriptPass } std::string techmap_args = "-map +/ecp5/latches_map.v"; if (abc9) - techmap_args += " -map +/ecp5/abc_map.v"; + techmap_args += " -map +/ecp5/abc_map.v -max_iter 1"; run("techmap " + techmap_args); if (abc9) { - run("read_verilog -icells -lib +/ecp5/abc_model.v"); if (nowidelut) run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200"); else -- cgit v1.2.3 From 6b1b03d9f771addbd54358299faad181b589c9f8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 19:20:17 -0700 Subject: ecp5: remove DPR16X4 from abc_unmap.v --- techlibs/ecp5/abc_unmap.v | 20 -------------------- 1 file changed, 20 deletions(-) (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc_unmap.v index 0f918c202..d43cdd93f 100644 --- a/techlibs/ecp5/abc_unmap.v +++ b/techlibs/ecp5/abc_unmap.v @@ -3,23 +3,3 @@ module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y); assign Y = A; endmodule - -module \$__ABC_DPR16X4_SEQ ( - input [3:0] DI, - input [3:0] WAD, - input WRE, - input WCK, - input [3:0] RAD, - output [3:0] DO -); - parameter WCKMUX = "WCK"; - parameter WREMUX = "WRE"; - parameter [63:0] INITVAL = 64'h0000000000000000; - - TRELLIS_DPR16X4 #( - .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL) - ) _TECHMAP_REPLACE_ ( - .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK), - .RAD(RAD), .DO(DO) - ); -endmodule -- cgit v1.2.3 From 85d39653ac62fa4f1f809fb71b0df82a8bd01dfc Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 13:20:29 -0700 Subject: Remove unused model --- techlibs/ecp5/abc_model.v | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v index 4eb923cb1..56a733b75 100644 --- a/techlibs/ecp5/abc_model.v +++ b/techlibs/ecp5/abc_model.v @@ -3,16 +3,3 @@ (* abc_box_id=2 *) module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y); endmodule - -module \$__ABC_DPR16X4_SEQ ( - input [3:0] DI, - input [3:0] WAD, - input WRE, - input WCK, - input [3:0] RAD, - output [3:0] DO -); - parameter WCKMUX = "WCK"; - parameter WREMUX = "WRE"; - parameter [63:0] INITVAL = 64'h0000000000000000; -endmodule -- cgit v1.2.3 From 455da572723e4f19ddc1d636b700a5fe1e975fbb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 13:21:21 -0700 Subject: Fix spacing --- techlibs/ecp5/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index e2bf3c854..01b10f392 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -116,7 +116,7 @@ module TRELLIS_DPR16X4 ( input WCK, input [3:0] RAD, /* (* abc_arrival= *) */ - output [3:0] DO + output [3:0] DO ); parameter WCKMUX = "WCK"; parameter WREMUX = "WRE"; -- cgit v1.2.3 From 696f854801619644e42f437894847ace96594a6b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 2 Sep 2019 12:15:11 -0700 Subject: Rename box --- techlibs/ecp5/abc_5g.box | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box index 66ebe196a..a336b4a85 100644 --- a/techlibs/ecp5/abc_5g.box +++ b/techlibs/ecp5/abc_5g.box @@ -18,7 +18,7 @@ CCU2C 1 1 9 3 # Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram) # Outputs: DO0, DO1, DO2, DO3 # name ID w/b ins outs -$__ABC_RAM16X2_COMB 2 0 8 4 +$__ABC_DPR16X4_COMB 2 0 8 4 #A0 A1 A2 A3 RAD0 RAD1 RAD2 RAD3 0 0 0 0 141 379 275 379 -- cgit v1.2.3