From 5aa8d7ceeb663be24c7b815822d0de2ee25431a6 Mon Sep 17 00:00:00 2001 From: Diego H Date: Mon, 2 Sep 2019 17:43:27 -0500 Subject: Updating gowin --- techlibs/gowin/arith_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/gowin/arith_map.v') diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v index e15de6423..af805b254 100644 --- a/techlibs/gowin/arith_map.v +++ b/techlibs/gowin/arith_map.v @@ -45,7 +45,7 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO); genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice - ALU #(.ALU_MODE(32'b0)) + ALU #(.ALU_MODE(0)) alu(.I0(AA[i]), .I1(BB[i]), .I3(1'b0), -- cgit v1.2.3 From af7bdd598e017b0e8887d893c901ae93935d20b2 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 21 Oct 2019 12:00:27 +0200 Subject: use ADDSUB ALU mode to remove inverters --- techlibs/gowin/arith_map.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'techlibs/gowin/arith_map.v') diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v index af805b254..b6f9e8c38 100644 --- a/techlibs/gowin/arith_map.v +++ b/techlibs/gowin/arith_map.v @@ -40,15 +40,15 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); wire [Y_WIDTH-1:0] AA = A_buf; - wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + wire [Y_WIDTH-1:0] BB = B_buf; wire [Y_WIDTH-1:0] C = {CO, CI}; genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice - ALU #(.ALU_MODE(0)) + ALU #(.ALU_MODE(2)) // ADDSUB I3 ? add : sub alu(.I0(AA[i]), .I1(BB[i]), - .I3(1'b0), + .I3(~BI), .CIN(C[i]), .COUT(CO[i]), .SUM(Y[i]) -- cgit v1.2.3