From 5aa8d7ceeb663be24c7b815822d0de2ee25431a6 Mon Sep 17 00:00:00 2001 From: Diego H Date: Mon, 2 Sep 2019 17:43:27 -0500 Subject: Updating gowin --- techlibs/gowin/synth_gowin.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/gowin/synth_gowin.cc') diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index ac3dbfb29..1fc029e3c 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -226,7 +226,7 @@ struct SynthGowinPass : public ScriptPass if (check_label("vout")) { if (!vout_file.empty() || help_mode) - run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix gen %s", + run(stringf("write_verilog -nohex -decimal -attr2comment -defparam -renameprefix gen %s", help_mode ? "" : vout_file.c_str())); } } -- cgit v1.2.3 From ec56438cf29c6cfdad5cc28987298ec6bd363d47 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Wed, 4 Sep 2019 10:33:47 +0200 Subject: gowin: add splitnets to appease the PnR --- techlibs/gowin/synth_gowin.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs/gowin/synth_gowin.cc') diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index ac3dbfb29..9c2a5c837 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -186,6 +186,7 @@ struct SynthGowinPass : public ScriptPass run("techmap -map +/techmap.v"); if (retime || help_mode) run("abc -dff", "(only if -retime)"); + run("splitnets"); } if (check_label("map_ffs")) -- cgit v1.2.3 From ae93c034adc8a7d14a9f39175dacdddda75ea7a2 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Wed, 4 Sep 2019 16:29:40 +0200 Subject: set undriven pads to zero --- techlibs/gowin/synth_gowin.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs/gowin/synth_gowin.cc') diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 0bfa9da1a..f7a5006bc 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -210,6 +210,7 @@ struct SynthGowinPass : public ScriptPass if (check_label("map_cells")) { run("techmap -map +/gowin/cells_map.v"); + run("setundef -undriven -zero"); run("hilomap -hicell VCC V -locell GND G"); run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)"); run("dffinit -ff DFF Q INIT"); -- cgit v1.2.3 From 3eff2271d0fe25632f7e6b22cf0be078d2cd9990 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Thu, 5 Sep 2019 13:36:41 +0200 Subject: add MUX support --- techlibs/gowin/synth_gowin.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs/gowin/synth_gowin.cc') diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index f7a5006bc..4d32f62d4 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -196,6 +196,7 @@ struct SynthGowinPass : public ScriptPass run("opt_clean"); if (!nodffe) run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*"); + run("muxcover -mux4"); run("techmap -map +/gowin/cells_map.v"); run("opt_expr -mux_undef"); run("simplemap"); -- cgit v1.2.3 From 7a43be5e431f7518203b37bad2eb9ffb3b74add4 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Thu, 5 Sep 2019 16:38:47 +0200 Subject: use singleton ground and vcc nets, apparently this makes pnr happier --- techlibs/gowin/synth_gowin.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/gowin/synth_gowin.cc') diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 4d32f62d4..3581d050e 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -212,7 +212,7 @@ struct SynthGowinPass : public ScriptPass { run("techmap -map +/gowin/cells_map.v"); run("setundef -undriven -zero"); - run("hilomap -hicell VCC V -locell GND G"); + run("hilomap -singleton -hicell VCC V -locell GND G"); run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)"); run("dffinit -ff DFF Q INIT"); run("clean"); -- cgit v1.2.3 From 47374a495d3cbfa424cbe312aa4762e7c4e855ff Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Thu, 5 Sep 2019 17:25:51 +0200 Subject: support bram initialisation --- techlibs/gowin/synth_gowin.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/gowin/synth_gowin.cc') diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 3581d050e..cfddcec12 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -229,7 +229,7 @@ struct SynthGowinPass : public ScriptPass if (check_label("vout")) { if (!vout_file.empty() || help_mode) - run(stringf("write_verilog -nohex -decimal -attr2comment -defparam -renameprefix gen %s", + run(stringf("write_verilog -decimal -attr2comment -defparam -renameprefix gen %s", help_mode ? "" : vout_file.c_str())); } } -- cgit v1.2.3 From 96efa63f16ae30927759b374c86a68753199d0d2 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Fri, 6 Sep 2019 10:55:04 +0200 Subject: fix BRAM width and init --- techlibs/gowin/synth_gowin.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/gowin/synth_gowin.cc') diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index cfddcec12..f67627e8a 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -211,7 +211,7 @@ struct SynthGowinPass : public ScriptPass if (check_label("map_cells")) { run("techmap -map +/gowin/cells_map.v"); - run("setundef -undriven -zero"); + run("setundef -undriven -params -zero"); run("hilomap -singleton -hicell VCC V -locell GND G"); run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)"); run("dffinit -ff DFF Q INIT"); -- cgit v1.2.3 From 2fb20f184aad4e0286afb6b44712cf5bffb531f4 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Fri, 6 Sep 2019 11:28:17 +0200 Subject: Revert "add MUX support" It turns out that they make everything worse and they don't PnR. This reverts commit 3eff2271d0fe25632f7e6b22cf0be078d2cd9990. --- techlibs/gowin/synth_gowin.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'techlibs/gowin/synth_gowin.cc') diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index f67627e8a..e93225fab 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -196,7 +196,6 @@ struct SynthGowinPass : public ScriptPass run("opt_clean"); if (!nodffe) run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*"); - run("muxcover -mux4"); run("techmap -map +/gowin/cells_map.v"); run("opt_expr -mux_undef"); run("simplemap"); -- cgit v1.2.3 From f88335a8a5284a8e69230ec20eeeca6c02b055bf Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 28 Oct 2019 12:49:08 +0100 Subject: add wide luts --- techlibs/gowin/synth_gowin.cc | 96 +++++++++++++++++++++++++++---------------- 1 file changed, 60 insertions(+), 36 deletions(-) (limited to 'techlibs/gowin/synth_gowin.cc') diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index e93225fab..89cbc50ab 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -1,19 +1,19 @@ /* - * yosys -- Yosys Open SYnthesis Suite + * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2012 Clifford Wolf + * Copyright (C) 2012 Clifford Wolf * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ @@ -31,38 +31,44 @@ struct SynthGowinPass : public ScriptPass void help() YS_OVERRIDE { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" synth_gowin [options]\n"); + log(" synth_gowin [options]\n"); log("\n"); log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n"); log("\n"); - log(" -top \n"); - log(" use the specified module as top module (default='top')\n"); + log(" -top \n"); + log(" use the specified module as top module (default='top')\n"); log("\n"); - log(" -vout \n"); - log(" write the design to the specified Verilog netlist file. writing of an\n"); - log(" output file is omitted if this parameter is not specified.\n"); + log(" -vout \n"); + log(" write the design to the specified Verilog netlist file. writing of an\n"); + log(" output file is omitted if this parameter is not specified.\n"); log("\n"); - log(" -run :\n"); - log(" only run the commands between the labels (see below). an empty\n"); - log(" from label is synonymous to 'begin', and empty to label is\n"); - log(" synonymous to the end of the command list.\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); log("\n"); - log(" -nodffe\n"); - log(" do not use flipflops with CE in output netlist\n"); + log(" -nodffe\n"); + log(" do not use flipflops with CE in output netlist\n"); log("\n"); - log(" -nobram\n"); - log(" do not use BRAM cells in output netlist\n"); + log(" -nobram\n"); + log(" do not use BRAM cells in output netlist\n"); log("\n"); - log(" -nodram\n"); - log(" do not use distributed RAM cells in output netlist\n"); + log(" -nodram\n"); + log(" do not use distributed RAM cells in output netlist\n"); log("\n"); - log(" -noflatten\n"); - log(" do not flatten design before synthesis\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); log("\n"); - log(" -retime\n"); - log(" run 'abc' with -dff option\n"); + log(" -retime\n"); + log(" run 'abc' with -dff option\n"); + log("\n"); + log(" -nowidelut\n"); + log(" do not use muxes to implement LUTs larger than LUT4s\n"); + log("\n"); + log(" -abc9\n"); + log(" use new ABC9 flow (EXPERIMENTAL)\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -71,7 +77,7 @@ struct SynthGowinPass : public ScriptPass } string top_opt, vout_file; - bool retime, nobram, nodram, flatten, nodffe; + bool retime, nobram, nodram, flatten, nodffe, nowidelut, abc9; void clear_flags() YS_OVERRIDE { @@ -82,6 +88,8 @@ struct SynthGowinPass : public ScriptPass nobram = false; nodffe = false; nodram = false; + nowidelut = false; + abc9 = false; } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -128,6 +136,14 @@ struct SynthGowinPass : public ScriptPass flatten = false; continue; } + if (args[argidx] == "-nowidelut") { + nowidelut = true; + continue; + } + if (args[argidx] == "-abc9") { + abc9 = true; + continue; + } break; } extra_args(args, argidx, design); @@ -164,7 +180,7 @@ struct SynthGowinPass : public ScriptPass run("synth -run coarse"); } - if (!nobram && check_label("bram", "(skip if -nobram)")) + if (!nobram && check_label("bram", "(skip if -nobram)")) { run("memory_bram -rules +/gowin/bram.txt"); run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v"); @@ -203,7 +219,15 @@ struct SynthGowinPass : public ScriptPass if (check_label("map_luts")) { - run("abc -lut 4"); + if (nowidelut && abc9) { + run("abc9 -lut 4"); + } else if (nowidelut && !abc9) { + run("abc -lut 4"); + } else if (!nowidelut && abc9) { + run("abc9 -lut 4:8"); + } else if (!nowidelut && !abc9) { + run("abc -lut 4:8"); + } run("clean"); } -- cgit v1.2.3 From 293b2c2de5c127d860d9ce0c7ac98908fa053520 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 28 Oct 2019 12:57:12 +0100 Subject: undo formatting fuckup --- techlibs/gowin/synth_gowin.cc | 50 +++++++++++++++++++++---------------------- 1 file changed, 25 insertions(+), 25 deletions(-) (limited to 'techlibs/gowin/synth_gowin.cc') diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 89cbc50ab..a44bbe2f6 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -33,42 +33,42 @@ struct SynthGowinPass : public ScriptPass { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" synth_gowin [options]\n"); + log(" synth_gowin [options]\n"); log("\n"); log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n"); log("\n"); - log(" -top \n"); - log(" use the specified module as top module (default='top')\n"); + log(" -top \n"); + log(" use the specified module as top module (default='top')\n"); log("\n"); - log(" -vout \n"); - log(" write the design to the specified Verilog netlist file. writing of an\n"); - log(" output file is omitted if this parameter is not specified.\n"); + log(" -vout \n"); + log(" write the design to the specified Verilog netlist file. writing of an\n"); + log(" output file is omitted if this parameter is not specified.\n"); log("\n"); - log(" -run :\n"); - log(" only run the commands between the labels (see below). an empty\n"); - log(" from label is synonymous to 'begin', and empty to label is\n"); - log(" synonymous to the end of the command list.\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); log("\n"); - log(" -nodffe\n"); - log(" do not use flipflops with CE in output netlist\n"); + log(" -nodffe\n"); + log(" do not use flipflops with CE in output netlist\n"); log("\n"); - log(" -nobram\n"); - log(" do not use BRAM cells in output netlist\n"); + log(" -nobram\n"); + log(" do not use BRAM cells in output netlist\n"); log("\n"); - log(" -nodram\n"); - log(" do not use distributed RAM cells in output netlist\n"); + log(" -nodram\n"); + log(" do not use distributed RAM cells in output netlist\n"); log("\n"); - log(" -noflatten\n"); - log(" do not flatten design before synthesis\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); log("\n"); - log(" -retime\n"); - log(" run 'abc' with -dff option\n"); + log(" -retime\n"); + log(" run 'abc' with -dff option\n"); log("\n"); - log(" -nowidelut\n"); - log(" do not use muxes to implement LUTs larger than LUT4s\n"); + log(" -nowidelut\n"); + log(" do not use muxes to implement LUTs larger than LUT4s\n"); log("\n"); - log(" -abc9\n"); - log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log(" -abc9\n"); + log(" use new ABC9 flow (EXPERIMENTAL)\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -237,7 +237,7 @@ struct SynthGowinPass : public ScriptPass run("setundef -undriven -params -zero"); run("hilomap -singleton -hicell VCC V -locell GND G"); run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)"); - run("dffinit -ff DFF Q INIT"); + run("dffinit -ff DFF Q INIT"); run("clean"); } -- cgit v1.2.3 From c1921b45619fbca4cbcafe3cd9cfdc0fe29e251c Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 28 Oct 2019 13:01:20 +0100 Subject: really really fix formatting maybe --- techlibs/gowin/synth_gowin.cc | 82 +++++++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 41 deletions(-) (limited to 'techlibs/gowin/synth_gowin.cc') diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index a44bbe2f6..a95d81bfd 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -32,46 +32,46 @@ struct SynthGowinPass : public ScriptPass void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" synth_gowin [options]\n"); - log("\n"); - log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n"); - log("\n"); - log(" -top \n"); - log(" use the specified module as top module (default='top')\n"); - log("\n"); - log(" -vout \n"); - log(" write the design to the specified Verilog netlist file. writing of an\n"); - log(" output file is omitted if this parameter is not specified.\n"); - log("\n"); - log(" -run :\n"); - log(" only run the commands between the labels (see below). an empty\n"); - log(" from label is synonymous to 'begin', and empty to label is\n"); - log(" synonymous to the end of the command list.\n"); - log("\n"); - log(" -nodffe\n"); - log(" do not use flipflops with CE in output netlist\n"); - log("\n"); - log(" -nobram\n"); - log(" do not use BRAM cells in output netlist\n"); - log("\n"); - log(" -nodram\n"); - log(" do not use distributed RAM cells in output netlist\n"); - log("\n"); - log(" -noflatten\n"); - log(" do not flatten design before synthesis\n"); - log("\n"); - log(" -retime\n"); - log(" run 'abc' with -dff option\n"); - log("\n"); - log(" -nowidelut\n"); - log(" do not use muxes to implement LUTs larger than LUT4s\n"); - log("\n"); - log(" -abc9\n"); - log(" use new ABC9 flow (EXPERIMENTAL)\n"); - log("\n"); - log("\n"); - log("The following commands are executed by this synthesis command:\n"); + log("\n"); + log(" synth_gowin [options]\n"); + log("\n"); + log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n"); + log("\n"); + log(" -top \n"); + log(" use the specified module as top module (default='top')\n"); + log("\n"); + log(" -vout \n"); + log(" write the design to the specified Verilog netlist file. writing of an\n"); + log(" output file is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); + log("\n"); + log(" -nodffe\n"); + log(" do not use flipflops with CE in output netlist\n"); + log("\n"); + log(" -nobram\n"); + log(" do not use BRAM cells in output netlist\n"); + log("\n"); + log(" -nodram\n"); + log(" do not use distributed RAM cells in output netlist\n"); + log("\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); + log("\n"); + log(" -retime\n"); + log(" run 'abc' with -dff option\n"); + log("\n"); + log(" -nowidelut\n"); + log(" do not use muxes to implement LUTs larger than LUT4s\n"); + log("\n"); + log(" -abc9\n"); + log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log("\n"); + log("\n"); + log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } @@ -237,7 +237,7 @@ struct SynthGowinPass : public ScriptPass run("setundef -undriven -params -zero"); run("hilomap -singleton -hicell VCC V -locell GND G"); run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)"); - run("dffinit -ff DFF Q INIT"); + run("dffinit -ff DFF Q INIT"); run("clean"); } -- cgit v1.2.3 From 2f5e9e9885df0011a3b70b0ab64f54fcd33ce347 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 28 Oct 2019 13:10:12 +0100 Subject: More formatting --- techlibs/gowin/synth_gowin.cc | 104 ++++++++++++++++++++---------------------- 1 file changed, 49 insertions(+), 55 deletions(-) (limited to 'techlibs/gowin/synth_gowin.cc') diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index a95d81bfd..e9b2ccded 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -1,19 +1,19 @@ /* - * yosys -- Yosys Open SYnthesis Suite + * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2012 Clifford Wolf + * Copyright (C) 2012 Clifford Wolf * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ @@ -31,47 +31,41 @@ struct SynthGowinPass : public ScriptPass void help() YS_OVERRIDE { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" synth_gowin [options]\n"); - log("\n"); - log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n"); - log("\n"); - log(" -top \n"); - log(" use the specified module as top module (default='top')\n"); - log("\n"); - log(" -vout \n"); - log(" write the design to the specified Verilog netlist file. writing of an\n"); - log(" output file is omitted if this parameter is not specified.\n"); - log("\n"); - log(" -run :\n"); - log(" only run the commands between the labels (see below). an empty\n"); - log(" from label is synonymous to 'begin', and empty to label is\n"); - log(" synonymous to the end of the command list.\n"); - log("\n"); - log(" -nodffe\n"); - log(" do not use flipflops with CE in output netlist\n"); - log("\n"); - log(" -nobram\n"); - log(" do not use BRAM cells in output netlist\n"); - log("\n"); - log(" -nodram\n"); - log(" do not use distributed RAM cells in output netlist\n"); - log("\n"); - log(" -noflatten\n"); - log(" do not flatten design before synthesis\n"); - log("\n"); - log(" -retime\n"); - log(" run 'abc' with -dff option\n"); - log("\n"); - log(" -nowidelut\n"); - log(" do not use muxes to implement LUTs larger than LUT4s\n"); - log("\n"); - log(" -abc9\n"); - log(" use new ABC9 flow (EXPERIMENTAL)\n"); - log("\n"); - log("\n"); - log("The following commands are executed by this synthesis command:\n"); + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" synth_gowin [options]\n"); + log("\n"); + log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n"); + log("\n"); + log(" -top \n"); + log(" use the specified module as top module (default='top')\n"); + log("\n"); + log(" -vout \n"); + log(" write the design to the specified Verilog netlist file. writing of an\n"); + log(" output file is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); + log("\n"); + log(" -nodffe\n"); + log(" do not use flipflops with CE in output netlist\n"); + log("\n"); + log(" -nobram\n"); + log(" do not use BRAM cells in output netlist\n"); + log("\n"); + log(" -nodram\n"); + log(" do not use distributed RAM cells in output netlist\n"); + log("\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); + log("\n"); + log(" -retime\n"); + log(" run 'abc' with -dff option\n"); + log("\n"); + log("\n"); + log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } @@ -180,7 +174,7 @@ struct SynthGowinPass : public ScriptPass run("synth -run coarse"); } - if (!nobram && check_label("bram", "(skip if -nobram)")) + if (!nobram && check_label("bram", "(skip if -nobram)")) { run("memory_bram -rules +/gowin/bram.txt"); run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v"); @@ -237,7 +231,7 @@ struct SynthGowinPass : public ScriptPass run("setundef -undriven -params -zero"); run("hilomap -singleton -hicell VCC V -locell GND G"); run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)"); - run("dffinit -ff DFF Q INIT"); + run("dffinit -ff DFF Q INIT"); run("clean"); } -- cgit v1.2.3 From 903f9973913371452005eb173ac50fec1d5d1447 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 28 Oct 2019 15:18:01 +0100 Subject: add tristate buffer and test --- techlibs/gowin/synth_gowin.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/gowin/synth_gowin.cc') diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index e9b2ccded..d541edd84 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -174,7 +174,7 @@ struct SynthGowinPass : public ScriptPass run("synth -run coarse"); } - if (!nobram && check_label("bram", "(skip if -nobram)")) + if (!nobram && check_label("bram", "(skip if -nobram)")) { run("memory_bram -rules +/gowin/bram.txt"); run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v"); @@ -230,7 +230,7 @@ struct SynthGowinPass : public ScriptPass run("techmap -map +/gowin/cells_map.v"); run("setundef -undriven -params -zero"); run("hilomap -singleton -hicell VCC V -locell GND G"); - run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)"); + run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O, -toutpad TBUF OEN:I:O", "(unless -noiopads)"); run("dffinit -ff DFF Q INIT"); run("clean"); -- cgit v1.2.3 From 0f6269b04c4a5f44b62021759507bcbe61a7c8d7 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 28 Oct 2019 15:33:05 +0100 Subject: add IOBUF --- techlibs/gowin/synth_gowin.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'techlibs/gowin/synth_gowin.cc') diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index d541edd84..a70ff93bb 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -230,7 +230,8 @@ struct SynthGowinPass : public ScriptPass run("techmap -map +/gowin/cells_map.v"); run("setundef -undriven -params -zero"); run("hilomap -singleton -hicell VCC V -locell GND G"); - run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O, -toutpad TBUF OEN:I:O", "(unless -noiopads)"); + run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O " + "-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)"); run("dffinit -ff DFF Q INIT"); run("clean"); -- cgit v1.2.3 From dd8c7e1ddda152e9c06d4b950564eb4aa1051c98 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 18 Nov 2019 14:25:46 +0100 Subject: add help for nowidelut and abc9 options --- techlibs/gowin/synth_gowin.cc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'techlibs/gowin/synth_gowin.cc') diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index a70ff93bb..bb6d44e00 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -64,6 +64,12 @@ struct SynthGowinPass : public ScriptPass log(" -retime\n"); log(" run 'abc' with -dff option\n"); log("\n"); + log(" -nowidelut\n"); + log(" do not use muxes to implement LUTs larger than LUT4s\n"); + log("\n"); + log(" -abc9\n"); + log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -173,7 +179,7 @@ struct SynthGowinPass : public ScriptPass { run("synth -run coarse"); } - + if (!nobram && check_label("bram", "(skip if -nobram)")) { run("memory_bram -rules +/gowin/bram.txt"); -- cgit v1.2.3 From 8ab412eb16b1d4f98117247bf85e0c37627ee459 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Tue, 19 Nov 2019 15:53:44 +0100 Subject: Remove dff init altogether The hardware does not actually support it. In reality it is always initialised to its reset value. --- techlibs/gowin/synth_gowin.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'techlibs/gowin/synth_gowin.cc') diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index bb6d44e00..3c1426414 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -238,7 +238,6 @@ struct SynthGowinPass : public ScriptPass run("hilomap -singleton -hicell VCC V -locell GND G"); run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O " "-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)"); - run("dffinit -ff DFF Q INIT"); run("clean"); } -- cgit v1.2.3